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The UWB mixer was simulated and designed with the aid of the Advanced Design System (ADS) simulation software from Agilent Technologies. It was fabricated with the 0.18-μm RF silicon CMOS semiconductor process fromTaiwan Semiconductor Manufacturing Company (TSMC). By employing bulk-injection and DTMOS techniques, the mixer’s supply voltage falls to 0.7 V and consumes only 0.71 mW power.

Simulated CG versus LO input power is plotted in Fig. 3, which shows maximum CG of 11.3 dB with an LO input power of +5 dBm and RF power of -30 dBm. Figure 4 shows the double-sideband (DSB) NF as a function of LO input power. From Fig. 4, it can be seen that the minimum NF can be achieved when LO input power is equal to +5 dBm, revealing that maximum conversion gain and minimum NF occur for LO input power level of +5 dBm.

3. The proposed mixer’s conversion gain is shown as a function of LO input power.

4. The new mixer’s double-sideband (DSB) noise figure is shown versus LO input power.

Figure 5 shows CG for RF input signals swept from 0.6 to 14 GHz. As Fig. 5 indicates, the mixer’s 3-dB RF bandwidth extends from 0.6 to 11.0 GHz (a 10.4-GHz 3-dB bandwidth) with a fixed IF output of 100 MHz. The optimum DC supply voltage (VDD) is about +0.7 VDC with a 1.02 mA drain current, and the output buffers consume less than 0.02 mW for all measured results.

5. The proposed mixer’s conversion gain is plotted here as a function of RF input frequency.

Figure 6 shows the DSB NF versus RF input frequency, which is 9.51 to 10.45 dB from 0.6 to 11.0 GHz. Figure 7 shows that the input 1-dB compression point (P1dB) is approximately -15 dBm. Figure 8 shows the IIP3 performance, with simulated IIP3 of -5 dBm. Figure 9 shows the mixer’s circuit layout, with total chip area of 0.29 x 0.22 mm2, including the input and output pads. Table 2 summarizes the mixer’s performance, with comparisons to earlier designs.

6. The mixer’s double-sideband (DSB) noise figure is plotted here as a function of RF input frequency.

7. This plot shows the 1-dB-compression-point performance of the proposed mixer.

8. This plot shows the input-third-order-intercept (IIP3) performance of the proposed mixer.

9. This photograph shows the circuit layout for the new mixer.

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