Reference spurious signals can occur in a phase-lock-loop (PLL) system due to a charge pump or operational-amplifier (opamp) leakage current. By knowing how to predict the levels of these unwanted spurious signals, the process of picking optimum loop parameters is greatly simplified during the early stages of a PLL system design.

PLLs are commonly used with higher-frequency tunable oscillators, such as voltage-controlled oscillators (VCOs), to stabilize the phase and frequency of the tunable device to a lower-frequency oscillatorlike a temperature-compensated crystal oscillator (TCXO) or oven-controlled crystal oscillator (OCXO)using negative feedback. A typical application for such a setup is for a stable, high-frequency local-oscillator (LO) source.

Figure 1 shows the building blocks of a PLL system used for generating an LO signal. The PLL integrated circuit (IC) usually contains the reference (R) and feedback (N) dividers, the phase/frequency detector (PFD), and the charge pump, represented by the two current sources, ICP_UP and ICP_DN. The VCO output is compared to the reference clock (such as the OCXO output) after both signals are divided down in frequency by their respective integer dividers (N and R, respectively). The PFD block controls the charge pump to sink or source current pulses at the PFD frequency rate, f_{PFD}, into the loop filter to adjust the voltage on the tuning port of the VCO (V_Tune) until the outputs of the clock dividers are equal in frequency and are in phase. When these are equal, the PLL is considered locked. The LO frequency is related to the reference frequency, f_{REF}, by the following equation:

f_{LO} = (N/R)(f_{REF})

Figure 1 shows a PLL that is called an integer-N PLL because the feedback divider (the N-divider) can only assume integer values. When this divider can assume both integer and non-integer values, the loop is called a fractional-N PLL. The focus in this article will be only on integer-N PLLs, as different mechanisms are at work in fractional-N PLLs.

A PLL IC contributes its own nonideal characteristics to a system, such as phase noise and spurious content. The PLL system of Fig. 1 acts as a lowpass filter on the reference clock phase noise and as a highpass filter on the VCO's phase noise. The lowpass and highpass filter cutoff frequencies are defined by the loop bandwidth (LBW) of the PLL. Ideally, the LO phase noise follows that of the reference clock converted to the LO frequency (that is, multiplied by N/R) to the LBW and subsequently follows the phase noise of the VCO. The PLL IC's noise contribution elevates the phase noise in the transition area.

Figure 2 is a phase-noise plot generated by PLLWizard, a PLL design and simulation tool available at no charge from Linear Technology. Figure 2 shows both the total output phase noise ("Total"), and the individual noises at the output due to the reference ("Ref @ RF") and the VCO ("VCO @ RF"). The IC's noise contribution can easily be seen.

Any unwanted signals on the power supplies shown in Figure 1 (V_OCXO, V_CP, and V_VCO) can translate into spurious (spurs) on the LO signal. Careful design of these supplies greatly reduces or even eliminates these spurious signals. Charge pump related spurious signals, however, are inevitable. Still, they can be reduced with careful PLL system design. These spurious signals are commonly referred to as reference spurs, which here refers to f_{PFD}. An LO signal produced by an integer-N PLL has dual sideband spurious content at f_{PFD} and its harmonics.

Figure 3 shows the spectrum of a 2.1-GHz LO signal. Here, f_{PFD} is 1 MHz (N = 2100) and the reference clock is 10 MHz (R = 10). The loop bandwidth is 40 kHz. It is worth mentioning that the spurious level achieved in this measurement is outstanding due to the high performance of the LTC6945, which is a low-noise, low-spurious PLL IC from Linear Technology.

In steady-state operation, the PLL is locked and, theoretically, there is no more need to engage the ICP_UP and ICP_DN current sources of Fig. 1 during every PFD cycle. However, doing this would create a "dead zone" in the loop response, as there is a significant drop in the small-signal loop gain (practically an open loop). This dead zone is eliminated by forcing ICP_UP and ICP_DN to produce extremely narrow pulses during every PFD cycle. These are commonly referred to as anti-backlash pulses. This produces energy content on the VCO tune line at f_{PFD} and its harmonics. The negative feedback cannot counteract these pulses since these frequencies are outside the loop bandwidth of a properly designed PLL. The VCO, then, is frequency modulated (FM) by this energy content, and related spurious products appear at fPFD and its harmonics, all centered around the LO frequency.

Between anti-backlash pulses, the charge pump current sources are off (in tristate mode). Inherently, the charge pump has some leakage current when in tristate mode. Using an opamp in an active loop filter introduces yet another leakage current source due to the opamp's input bias and offset currents. The aggregate of these unwanted currents, whether sourcing or sinking, causes a drift in the voltage across the loop filter and, consequently, in the VCO's tuning voltage. The negative feedback of the loop will correct for this anomaly by introducing a unipolar current pulse from the charge pump once every PFD cycle so that the average tune line voltage produces the correct frequency out of the VCO. The pulses produce energy at f_{PFD}, which also causes spurious signals to appear centered around LO and offset by f_{PFD} and its harmonics, as previously noted.

In integer-N PLLs, frequency f_{PFD} is often chosen to be relatively small because of the system's frequency step size requirements. This means that the anti-backlash pulse width, especially with the present high-speed IC technologies, is extremely small compared to the PFD period. As such, a large leakage current causes the total charge pump pulses to be unipolar and tends to be the dominant cause of reference spurious signals.

In a particular communications frequency band there are multiple channels that occupy equal bandwidths. The center-to-center frequency distance between two adjacent channels is equal among all channels and is denoted by channel spacing. Due to several factors, it is common to find large variations in signal strength between any two adjacent channels. Figure 4 shows a typical scenario in a multichannel wireless communications system, whereby a stronger channel exists adjacent to a desired but weaker channel.

In an integer-N PLL, f_{PFD} is usually chosen to be equal to the channel spacing, which means that the reference spurious signals are positioned at the channel spacing from the LO. These spurious signals translate all adjacent and nearby channels to the center of the intermediate frequency (f_{IF}) signal along with the LO mixing the desired channel to the same frequency. These undesired channels appear as an elevated noise floor to the desired signal and limit the signal-to-noise ratio (SNR).

The mathematical prediction of a PLL IC's phase-noise contribution is relatively straightforward and can be accurately determined by calculations. However, the prediction of reference spurious levels is traditionally believed to be complex. This section derives a method to accurately predict reference spur levels due to leakage current using simple calculations.

Figure 5 shows a PLL system with a typical passive loop filter along with a current source denoted I_Leakage to represent the leakage current of the charge pump. Assuming the PLL is locked, I_Leakage reduces the charge held by capacitor C_{P} during the time when the charge pump is off. When the charge pump turns on once every PFD cycle, ICP_UP replenishes the charge lost from C_{P} by applying a short pulse of current. Feedback forces the average voltage seen at V_Tune (V_Tune_Avg) to be constant, maintaining the correct LO frequency. Figure 6 depicts this.

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The derivation of the resultant spurious signals involves some knowledge of loop stability requirements, the first being LBW restrictions. The LBW of the PLL system is designed to be at least 10 times smaller than f_{PFD}:

LBW = f_{PFD}/10.

Thus, the period of the PFD is:

T_{PFD} = 1/f_{PFD}

and hence:

LBW = 1/10T_{PFD}.

To create a stable loop with plenty of phase margin, a zero, consisting of resistance R_{Z} and capacitance C_{I} in Fig. 5, is inserted in the loop at about one-third the value of the LBW. That is:

Zero Location LBW/3 = 1/2pt_{Z} ? LBW 3/2pt_{Z}, where t_{Z} = R_{Z}C_{I}

Replacing LBW in the last equation with its equivalent in terms of the phase/frequency detector time period, T_{PFD}, results in:

3/2pt_{Z} = 1/(10T_{PFD}) or T_{PFD} = (2p/30)t_{Z}

This means that the PFD period is almost five times shorter than the time constant of the zero, t_{Z}. The implication is that the ripple produced at a period of T_{PFD }across C_{P} is mostly unseen by C_{I}. The closed-loop bandwidth LBW is approximately equal to the unity crossing of the open-loop gain. Since the zero is located within the loop bandwidth (it is located at one-third the unity crossing of the open-loop gain), the voltage across C_{I} is dictated by the negative feedback and is mostly a DC value. Practically speaking, only C_{P} is discharged and charged during the PFD cycles shown in Fig. 6.

If a capacitor, C, is charged or discharged with a constant current source, I, over a period of time given by ?T, the voltage delta across this capacitor is given by:

?V = I(?T/C)

To maintain a fixed output frequency at LO, the voltage droop that occurs during the discharge period is equal to the voltage buildup during the charging period of Fig. 6. That is:

V_Pk-Pk = I_Leakage(T_{Discharge})/C_{P}= I_CP(T_{Charge})/C_{P}

where:

T_{Charge} = the amount of time the charge pump current is active during every PFD cycle.

The charge pump current, I_CP, is usually in the mA range and leakage current, I_Leakage, is usually in the nA range, which means that:

T_{Charge} << T_{PFD} and T_{Discharge} T_{PFD}

This implies that the ripple voltage seen across C_{P} can be represented by a sawtooth waveform.

To study the effect of this sawtooth waveform on the spectrum of the LO signal, and since the waveform is a periodic function, it can be broken down into its frequency components using Fourier Series analysis:

where:

V_Pk-Pk = (I_Leakage)T_{PFD}/C_{P} = (I_Leakage)/C_{Pf}P_{FD}

When n = 1, the fundamental peak is:

Vpk-Fund = I_Leakage/(pCPfPFD)

and the second-harmonic peak is:

V_{pk-2ndHar} = I_Leakage/(2pC_{P}f_{PFD})

and so on.

The DC value, which is equal to V_Tune_Avg in Fig. 6, is set by the negative feedback per the requested LO frequency. The AC components, however, frequency modulate the VCO through its tune pin with a tuning sensitivity of K_{VCO} to produce dual sideband spurious content with a fundamental of f_{PFD}. The Appendix derives the following equation for the sideband/carrier ratio:

Sideband/Carrier = 20log_{10} (K_{VCO}E_{m}/ 2f_{m})

The effect of the negative feedback on these AC components is negligible because f_{PFD}, being the fundamental and the lowest frequency component, is at least 10 times higher in frequency than the zero-dB crossing of the open-loop gain by design.

To find the fundamental reference spur-to-carrier power ratio, f_{m} = f_{PFD}, E_{m} = V_{pk-Fund}, and:

Ref_Spur_Fund/Carrier = 20log_{10}(K_{VCO}I _Leakage/2pC_{P}f_{PFD}^{2}) dBc

For the second-harmonic reference spurious product, f_{m} = 2f_{PFD}, E_{m} = V_{pk-2ndHar}, and:

Ref_Spur_2ndHar/Carrier = 20log_{10} (K_{VCO}I_Leakage/8pC_{P}f_{PFD}^{2}) dBc

The ratios for higher-order harmonics are found using a similar approach.

Figure 7 shows an example implementation of an active loop filter built around an opamp. Current I_Leakage represents the combined leakage currents of the charge pump and the opamp. The same methodology used in the passive filter example applies here since the loop filters have a similar structure. The addition of the pole composed of R_{P2} and C_{P2} at the output of the opamp to limit the device's contribution of noise beyond 15 or 20 times the LBW reduces the amplitude of the sawtooth signal seen at the tuning node of the VCO. It should be noted that capacitance C_{P2} includes the input capacitance of the VCO tuning port.

The sawtooth signal undergoes lowpass filtering, the equation for which can be found using basic voltage division equations in the Laplace Transform domain, and can be written as:

|V_Tune/V_Filt| = |1/(1 + j2pfR_{P2}C_{P2})|

where:

f = frequency (in Hz).

Naturally, the sawtooth signal Fourier Series components get affected differently according to their frequency. The reference spur-to-carrier ratios become:

Ref_Spur_Fund/Carrier = 20log_{10}VCOI _Leakage|V_Tune/V_Filt|_{1}/2_{p}C_{P}f_{PFD}^{2}> dBc

where:

|V_Tune/V_Filt|_{1} = |1/(1 + j2_{pfPFD}R_{P2} C_{P2}|

Ref_Spur_2ndHar/Carrier = 20log_{10}VCOI_Leakage |V_Tune/V_Filt|_{2}/8pC_{P}f_{PFD}^{2}> dBc

|V_Tune/V_Filt| = |1/(1 + j4pf_{PFD}R_{P2}C_{P2}|

and so on.

The PLL systems shown in Figs. 5 and 7 were reproduced in the laboratory. External current was introduced at the charge pump node using a precision source meter to null the intrinsic fundamental reference spur caused by inherent leakages in the system. Then, specific additional current values were injected into the loop while measuring the fundamental reference spurious levels.

Figure 8 compares the measured and calculated values for both filter types. The measured and calculated numbers agree to within the instrument accuracies and component tolerances. Table 1 presents more details about the PL systems used for the measurements of Fig. 8. Table 2 summarizes the equations derived in this article.

Integer-N PLL operation and nonidealities are important topics in the design of RF systems. Reference spurious signals can have a significantly negative impact on overall system performance. Thus, a simple yet accurate model to predict reference spurious levels can be a useful tool.

Appendix: Narrowband FM Equations Derive Spurious/Carrier Ratio

Consider an FM signal centered at an LO of frequency f_{c} in Hz. This signal can be written as:

e(t) = E_{c}cosct + ?(t)>,

where:

E_{c} = the peak amplitude of e(t) (in V).

The instantaneous frequency of e(t) is:

?_{inst} = (d/dt)ct + ?(t)> = 2pf_{c} + ?'(t) rad/s

Since e(t) is an FM signal, the modulating signal e_{m}(t) modulates the instantaneous frequency of e(t) as follows:

?'(t) = Ke_{m}(t) (in rad/s)

where:

K = the deviation sensitivity of frequency :

As far as this article is concerned, the modulating signal is a toneone of the Fourier series components of the sawtooth waveformwhich is given by:

e_{m} = E_{m}cos(2pf_{m}t)

where:

E_{m} = the peak amplitude of e_{m}(t) (in V)

and

fm = its frequency (in Hz).

This means that the time-varying component of e(t)'s phase is:

where:

K_{VCO} = the tuning sensitivity of the VCO used to generate e(t) (in Hz/V).

Parameter m is defined as the modulation index, such that:

?(t) = (K_{VCO}E_{m}/f_{m})sin(2pf_{m}t) = msin (2pfmt)

where:

m = K_{VCO}E_{m}/f_{m}

and e(t) can be written as:

e(t) = E_{c}cosct + msin(2pf_{m}t)>.

Using some basic trigonometric identities to expand this expression results in:

e(t) = E_{c} cos(2pf_{c}t)cosmt)> -E_{c}ct)>sinmt)>.

Parameter m is much smaller than 1 as far as the reference spurious generation is concerned, implying that:

cosmt)> 1

and:

sinmt)> msin(2pf_{m}t)

then:

e(t) E_{c}cos(2pf_{c}t)-mE_{c}sin(2pf_{c}t) sin(2pf_{m}t)

or:

e(t) = E_{c}cos(2pf_{c}t)+ 0.5mE_{c}(cosc + f_{m}) t> - cosc + f_{m})t>)

which is a narrowband FM signal composed of a carrier at f_{c} and two sidebands located at f_{m} centered around the carrier.

Based on the last representation of e(t), the sideband-to-carrier power ratio (in dBc) is given by:

Sideband/Carrier = 20log_{10}(m/2)

= 20log_{10}(K_{VCO}E_{m}/2f_{m})

**References**

- B.P. Lathi, Modern Digital and Analog Communication Systems, 3rd ed., Oxford University Press, Oxford, England,1998.
- F.M. Gardner, Phaselock Techniques, 3rd ed., Wiley, New York, 2005.
- Linear Technology, LTC6945 Datasheet, 1630 McCarthy Blvd., Milpitas, CA, 95035.
- R.E. Best, Phase-Locked Loops, Theory, Design, and Applications, 2nd ed., McGraw-Hill, New York, 1993.
- W.F. Egan, Frequency Synthesis by Phase Lock, 2nd ed., Wiley, New York, 2000.
- Z. Tranter, Principles of Communications, Systems, Modulation, and Noise, 4th ed., Wiley, New York, 1995.