Logic devices have improved in recent years due to advances in silicon germanium (SiGe), indium gallium phosphide (InGaP), and indium phosphide (InP) compound semiconductors. Microwave engineers may know these materials for their use in heterojunction bipolar transistors (HBTs). What they may not realize is that the increased switching speeds of HBTs, in conjunction with the unique nonsaturated operational mode of emitter-coupled logic (ECL), has encouraged their use in logic gates and other digital components.

These are used for the execution of binary arithmetic functions such as addition and multiplication. Further, binary storage is typically implemented using controlled state devices, referred to as flip-flops. The most common elementary logic devices are schematically illustrated in Fig. 1.

For a true output, or logic value of 1, the NAND gate requires that both logic inputs are present; this function is equivalent to binary multiplication. Similarly, for a true output, an exclusive OR (XOR) gate requires that the logic inputs are different; this function is equivalent to binary addition. The type-D flip-flopD for datais the most common flip-flop in use today. It is better known as data or delay flip-flop (as its output, Q, represents a delay of input D). Since the output (Q+) takes the value of the D input at the clock transition, it is often used for data synchronization.

The indicated logic devices have been in use for decades in their conventional technology implementations of silicon transistor-transistor logic (TTL) and complementary metal-oxide-semiconductor (CMOS). For very high-speed operation (e.g., 1000 MHz or more), ECL has been employed.1 With the advent of the HBT, the operational frequency of these logic devices has extended to beyond 50 GHz.2

Figure 2 illustrates the basic ECL building block and the input/output transfer characteristic. Q1 and Q2 form a high gain differential amplifier stage, while Q3 and Q4 provide a low output impedance buffer stage.3 The binary states of ECL devices are cutoff and linear; this avoids excess charge storage in the base region, which must be depleted before the transistor can change state. Another feature of the ECL structure is the differential or complementary output, which facilitates several of the microwave components (as will be demonstrated). A nominal input drive level for ECL switching is -10 dBm.4

With an appropriate voltage transition at the clock input, the D flip-flop transfers the data state at the D terminal to the Q+ output. If the D flip-flop is configured in accordance with the schematic of Fig. 3, the Q+ output will change state at one-half the clock frequency, thereby achieving frequency division by two.

The D flip-flop may also be utilized for the precise generation of quadrature signals, as illustrated in the schematic and timing diagram of Fig. 4. Another popular D flip-flop application is the wideband phase-frequency detector (PFD) shown in Fig. 5. Operation of the phase detector is quite simple: the input signal transitions cause the flip-flops to change state; a NAND gate feedback arrangement clears both flip-flops whenever the Q+ outputs are both in a high state. The differential voltage of the flip-flops is averaged using an operational amplifier with suitable lowpass filtering. The quadrature input signal condition is illustrated. A relative change of the input signal phase produces a linear change in the average output voltage. The dotted line of the graphic indicates the output voltage at 90 phase lead of the signal at FF1. The simplicity of circuit implementation and wideband operation suggests application in phase compensation of broadband EW receivers and angle-of-arrival determination, as well as cable phase compensation for a variety of equipment installations.5

Logic AND/OR gates are utilized in many digital applications for the implementation of Boolean algebra, to determine the status of specific events and to implement other logic functions. The exclusive OR/NOR gates are significant due to their unique ability to implement both digital and analog functions. Figure 6 illustrates the deployment of the XOR logic gate as a quadrature phase detector. The average differential voltage at the XOR gate output is a linear function of the phase difference of the input signals.

Matched differential outputs from the XOR logic gate will ensure zero voltage at the output of the operational amplifier when the input signals are in phase quadrature. Accuracy of quadrature signal amplitude and phase is significant in reducing system measurement error. The OR gate has been widely used as a lock detector in integrated-circuit (IC) phase-lock-loop (PLL) applications.

Quadrature input signals to the XOR logic gate produce frequency multiplication at the XOR output, as illustrated in Fig. 7. A balun transformer may be used at the output to convert the differential output to single-ended and thereby increase the output signal level. Figure 7(c) represents the output signal spectrum for a 5-GHz input at -10 dBm, while Fig. 7(d) displays the output spectrum for a 5.0-GHz input at 0 dBm. No tuning is required, and the fundamental and third-harmonic frequencies may be further suppressed with the addition of a low-order bandpass filter.

Figure 8 illustrates an XOR logic gate in a wideband comb spectrum generation application. The input signal at the B-input is delayed with respect to the A-input using a short length of cable, thereby producing an output pulse width approximately equal to the time delay of the cable. The output signal rise and fall times are typically 20 ps. The output power spectrum extends beyond 22 GHz and may be utilized for receiver calibration, phase-lock reference, and other applications.

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Benefits of comb spectrum generation using a logic XOR gate versus a step recovery diode are reduction in input drive power required to achieve the extended output spectrum, as well as a broad input signal operational bandwidth without tuning or impedance matching techniques. The XOR gate was implemented using m GaAs HBT technology and has a toggle rate of 13 Gb/s. XOR gates using InP HBT technology are capable of delivering comb spectrum output beyond 40 GHz.

Because the operation of the XOR gate is effectively multiplication of the input signals, it may be used in frequency translation applications in a similar manner to the ubiquitous microwave mixer in both up and down converter applications. Figure 9 illustrates a frequency-translation application where both the sum and difference frequencies are available at the respective outputs simultaneously. Also indicated in Fig. 9 is the 1.0-GHz intermediate-frequency (IF) output from a frequency downconverter with the A-input signal (F1) swept from 0.10 to 20.0 GHz at -8 dBm and the B-input signal (F2) swept from 1.1 to 21.0 GHz.7

Figure 10 shows how a wide-bandwidth constant phase limiter is readily implemented using an XOR gate. The intrinsic symmetry of the HBT differential amplifier configuration assures constant amplitude and phase at the output. The differential output may be converted to a single-ended configuration using a wideband balun. Amplitude limiting is initiated typically at a -20-dBm input level and may be readily extended using cascaded gates. For proper operation, the B-input is biased at the logic input transition voltage.

Figure 11 details how a wide-bandwidth balun is implemented using the XOR logic gate directly. The intrinsic symmetry of the HBT differential amplifier configuration assures constant amplitude and phase at the output. For proper operation, the B-input is biased at the logic input transition voltage.

Figure 12 shows how a simple balanced mixer is implemented using the XOR gate as a balun in conjunction with a pair of Schottky diodes, quarter-wavelength lines for the diode returns, and lumped-element inductor and capacitors. The intrinsic differential drive of the local oscillator (LO) provides high isolation from the LO to RF ports. The simple mixer is limited to moderate bandwidth applications.

Figure 13 shows the implementation of a balanced harmonic mixer for millimeter-wave applications. The quarter-wavelength lines are implemented at the LO frequency which is approximately one-half the RF frequency; therefore, the transmission lines are one-half-wavelength long at RF and provide a low impedance return for the RF signal.

Figure 14 reveals a wideband RF sampling circuit utilizing the narrow impulse generated at the XOR output due to delay between the signals at the A and B input. The balanced impulse drive at the XOR output momentarily turns on the Schottky diodes within the sampling bridge. At that time, the coupling capacitors charge to the instantaneous value at the RF input. The sampling aperture time is controlled by the input signal delay line.

Finally, a narrowband VCO (not shown) can be implemented with an XOR gate, single-section bandpass filter, and phase shifter to control the frequency. With the A-input biased at the logic transition threshold, a high-gain amplifier is realized. The discrete feedback loop, consisting of a single-section bandpass filter and variable phase-shift network, achieves the necessary conditions for oscillation at the center frequency of the bandpass filter.8 SiGe HBT gates can produce oscillation at X-band frequencies, while AlGaP and InP HBT gates can produce oscillations to 40 GHz. Because the HBT is intrinsically a low-noise device, low-noise oscillators may be constructed consistent with the loaded quality factor (Q) of the resonator. The output signal may be gated via control at the A-input or forcing the phase shift to a nonoscillation condition.


Acknowledgment

The author acknowledges and is grateful to Inphi Corp., Hittite Microwave Corp., and Iterra Communications for high-speed logic device sample boards.

References

  1. 1. For example, the toggle rate of the On Semiconductor model MC100LVEL29 D flip-flop is 1.0 Gb/s using silicon transistors.
  2. 2. For example, the toggle rate for the Hittite model HMC673LC3C D SiGe flip-flop is 13 Gb/s, while the Inphi 50700DF D InP flip-flop toggle rate is 50 Gb/s.
  3. 3. Negative supply bias is illustrated; however, positive supply bias devices are also available.
  4. 4. The input signal transition with for the emitter coupled pair is 0.115 V, peak-to-peak.
  5. 5. Although the input signals are indicated as square waves, the reader is advised that the actual input signal is sinusoidal in each case.
  6. 6. See the Inphi Corp. website at www.inphi.com for 50 GBPS XOR gate data sheet (50710XR).
  7. 7. Conversion loss test and data documentation are courtesy of Bert Henderson of Cobham Defense Systems, San Jose, CA (www.cobham.com).
  8. 8. United States Patent No. 7626464.

KENNETH V. PUGLIA
Principal, E x H Consulting Services
146 Westview Dr.
Westford, MA 01886
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e-mail: kvpuglia@verizon.net