Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.

Channel filtering for the receiver front end is performed in the IF blocks by means of passive filters with high selectivity.9 To prevent possible image-signal interference of desired signals, and to keep unwanted signals from jamming the receiver front end, an RF image-rejection filter is needed in the front end. A microstrip interdigital filter was adopted in this design due to advantages of simple structure, easy implementation, compact size, and low cost. Figure 3(a) shows the layout of the designed microstrip interdigital bandpass filter. Simulated responses for the filter design were obtained by means of ADS Momentum software simulation, and are plotted in Figs. 3(b) and (c).

Low-Cost Front End  Receives 9 GHz, Fig. 3(a)

Low-Cost Front End  Receives 9 GHz, Fig. 3(b)

Low-Cost Front End  Receives 9 GHz, Fig. 3(c)

As shown in Fig. 3(a), the bandpass filter consists of an array of quasi-TEM-mode transmission-line resonators, each of which has an electrical length of 90 deg. at the midband frequency and short-circuited at one end while open-circuited at the other end with alternative orientation. Tapped lines with a characteristic admittance equal to the source/load characteristic admittance are used for the filter’s input and output ports.8 The position of the input/output tapped line affects the filter’s matching.

The center frequency depends on lengths l1 and l2. Coupling is achieved by the fields fringing between adjacent resonators separated by spacings s1 and s2. Coupling grows stronger with narrower spacings, and the bandwidth increases. Spacings s1 and s2 have great influence on matching, so there are tradeoffs between the bandwidth and the reflection coefficient during the design process. As Figs. 3(b) and (c) show, the filters achieve excellent performance. The dimensions are detailed in Table 2.

Low-Cost Front End  Receives 9 GHz, Table 2

The performance of the LO module is important to the receiver front end. The LO module (Fig. 4) is composed of a frequency synthesizer integrated with a low-noise digital phase frequency detector (PFD) and a precision charge pump (CP), a passive third-order loop filter, and a voltage-controlled-oscillator (VCO) chip. The VCO provides the required frequency band and low-noise characteristics. A 10-MHz reference signal was provided to the LO module by a model SMF100A signal generator from Rohde & Schwarz, which was part of the test system. The phase-locked loop (PLL) for the receiver front end is designed for an output center frequency of 7 GHz. To ensure adequate LO signal power, an amplifier was added.

Low-Cost Front End  Receives 9 GHz, Fig. 4

Low-Cost Front End  Receives 9 GHz, Fig. 5

To maintain reliable high-speed digital wireless communications, LO phase noise should be minimized. Within the PLL’s loop bandwidth, the PLL phase detector is typically the dominant noise source; outside the loop bandwidth, the VCO noise is often the dominate noise source.10  Therefore, the loop bandwidth is optimized to improve the phase-noise performance. Figure 5 shows the measured phase-noise performance of the PLL used in the receiver front end. The phase noise is better than -70 dBc/Hz offset 1 kHz from the carrier, better than -80 dBc/Hz offset 10 kHz from the carrier, and better than -90 dBc/Hz offset 100 kHz from the carrier.

Download this article in .PDF format
This file type includes high resolution graphics and schematics when applicable.