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Schotty diode quadruplers provide practical means of generating signals at higher frequencies, especially when they can perform such functions with minimal conversion loss (CL). Lower loss generally means higher power levels at the output of the quadrupler. Fortunately, with the aid of a commercial computer-aided-engineering (CAE) software program, it has been possible to design a Schottky diode multiplier with low CL for applications requiring signals from 80 to 100 GHz. This monolithic frequency multiplier was fabricated with a 0.1-μm GaAs pseudomorphic-high-electron-mobility-transistor (pHEMT) process, providing as much as +2 dBm output power across its 20-GHz output bandwidth.

Due to their nonlinear characteristics, Schottky diodes are often the key elements in passive frequency multipliers. They are capable of producing stable, low-noise multiplied output signals when combined with an appropriate oscillator.1 Unfortunately, as the frequency increases, the dielectric circuit losses and roughness of the conductor surface can result in increases in the CL of a Schottky diode multiplier. As a result, one of the design goals when working with these components involves minimizing the CL.

A number of researchers have explored different approaches to passive multiplier designs,2-4 with the importance of impedance matching for the source and load impedances of the Schottky diodes detailed in ref. 2 (although an impedance-matching method or solution was not provided). A W-band frequency doubler was presented in ref. 3, with a quarter-wavelength short stub (at the fundamental frequency) used to provide a short circuit for the second-harmonic frequency at the input of the diode, and a quarter-wavelength open stub (at the fundamental frequency) used to short the fundamental frequency at the output of the diode. This study did not present the effects of these stubs on CL performance, however. A similar design approach was presented in ref. 4.

Work in ref. 5 detailed a method for optimizing the input and output impedances to a high-gain active frequency multiplier with reflector networks. A similar approach was used in ref. 6 to optimize a frequency tripler. A W-band active frequency doubler was designed and fabricated with a 0.15-μm InGaAs/InAlAs/GaAs mHEMT process in ref. 7. These reports offered several different approaches for designing high-frequency multipliers, but with little description of CL optimization methods for the passive balanced multipliers. The present report examines the importance of impedance matching for the input and output multiplier ports, using input and output reflector networks to not only impedance match to the impedances of the diodes, but also reduce the CL of the balanced multiplier.

Balanced quadrupler

One method of reducing the CL of a diode multiplier is to focus on the Schottky diode and its supporting circuitry. This can be done by examining the construction of a Schottky diode quadrupler, the design of the component’s balun, optimization of the input power network and the input/output reflector networks; optimizing the full quadrupler; and fabricating and testing the quadupler to check how the modeled results compare with actual performance. Figure 1 offers a block diagram of a generic balanced multiplier, with an antiparallel diode-pair structure used with a balanced-mixer configuration.8 In this configuration, only even-harmonic frequencies are available at the output, with inherent rejection fundamental-frequency and odd-harmonic signals at the output.

As Eq. 1 shows, the nonlinear Schottky diode current-voltage (I-V) curves are closely related to the input signal amplitude. The input power can be optimized to obtain minimum CL from the multiplier by analysis of Eq. 1:

I = I0[exp(VA/VT) – 1]   (1)

where:

I0= the reverse saturation current;

VA = the diode external voltage; and

VT = the thermopower voltage;

Equations 2 and 3 show that the signals reflected by different reflector networks have different phase characteristics. Short-circuit (SC) transmission-line voltage is a sinusoidal function, but open-circuit (OC) transmission-line voltage is a cosine function. Changing the type of transmission line can optimize the performance of the multiplier. The voltage of an SC transmission line can be found by studying Eq. 2, while the voltage of an OC transmission line can be calculated by Eq. 3:

V(d) = 2jV+sin(βd)   (2)

V(d) = 2V+cos(βd)   (3)

where:

V+ = the voltage amplitude of the electromagnetic (EM) wave propagating along the positive direction;

β = the phase constant of the transmission line; and

d = the length of the transmission line.

As a result, it is necessary to optimize the input-power network and the input/output reflection networks to minimize the CL of a high-frequency multiplier design.

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