Using Logic Analysis to Find Root Cause of Digital Design Errors

Sponsored by: Agilent Technologies

    Date & Time

  • This webinar is now available On-Demand.
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    Event Type

  • On-Demand Webinar

Speakers

Presented By:

Brad Frieden
Digital Debug Solutions Product Planner
Oscilloscope and Protocol Division
Agilent Technologies

Description

Why This Webcast is Important:
Quickly troubleshooting and validating a digital design can be complex as faster FPGAs, ASICs, and DSPs, require tools that allow engineers to easily access system functional behavior across a large number of input signals. A logic analyzer provides just the insight needed. The new generation of portable logic analyzers combine fast sample rates, deep memory, and high-speed, customizable trigger sequencers so that a root cause of failure can be found even far from the trigger point, thus accelerating the debug process. This Webcast will explore how the root-cause of functional and timing errors can be easily found by using a logic analyzer early in the debug process. Learn how to observe bus-level signal integrity to get a quick overview of possible design violations involving wide parallel buses. Different techniques will be shown to help you accelerate your digital system debug and validation process.

Who Should View this Webcast:
Digital Design, validation and test engineers who need to debug and validate fast, complex designs. Digital designs may include FPGAs, SOCs, embedded memories, and high-speed A/D and D/A converters.

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