Each year, those interested in electron devices have the opportunity to assess the true states of the art in device physics, process technologies, and modeling approaches. That opportunity takes place at the annual IEEE International Electron Devices Meeting (IEDM), scheduled for December 10- 12, 2007 in the Hilton Washington Hotel (Washington, DC). The IEDM is sponsored by the IEEE Electron Devices Society and features hundreds of technical presentations on devices, interconnections, and methods of modeling them. What follows is an "RF-centric" summary of key presentations to be made at the upcoming 2007 IEDM. For those interested in more than RF, such as memory, power electronics, nanotubes, and more, please visit the conference site at www.ieee.org/conference/iedm for additional details on the conference and its many technical sessions.

In a session on "Quantum, Power, and Compound Semiconductor Devices- II-V FETs for Microwave, Millimeter- Wave, and Digital Applications," R. Lai and associates from Northrop Grumman Space Technology (NGST, Redondo Beach, CA) and NASA’s Jet Propulsion Laboratory (Pasadena, CA) will share details on their study of indium-phosphide (InP) high-electron-mobility-transistor (HEMT) device technology. By fabricating sub-50-nm InGaAs/InAlAs/InP device structures, they were able to extrapolate maximum frequency of oscillation of above 1 THz with unilateral gain to 1.2 THz and maximum stable gain (MSG) to 1.1 THz.

To demonstrate the capabilities of the devices, they were installed in a threestage common-source low-noise monolithic- microwave-integrated-circuit (MMIC) amplifier. The amplifier achieved 6-dB gain per stage at 300 GHz and 5 dB gain per stage at 340 GHz. To further improve performance, device modifications on the baseline NGST InP HEMT process were applied, including the reduction of gate length from 70 ns to less than 50 nm using electron-beam lithography.

Following the refinements, on-wafer measurements were made on the lownoise MMIC amplifiers. They yielded 21 dB total amplifier gain at 285 GHz, with 18 dB total amplifier gain at 300 GHz and 15 dB amplifier gain at 340 GHz. The results closely match computer simulated values and are consistent with extrapolations based on measured S-parameter data through 110 GHz.

In the same session, Seong-Jin Yoon and associates from the Seoul National University, School of Electrical Engineering and Computer Science (Seoul, Korea) will present results on reducedgate- length InAlAs/InGaAs metamorphic HEMTs. The researchers had achieved cutoff frequency of 450 GHz for 28-nm-gate-length devices previously, and decided to scale their devices further, aiming for transistors with 15- nm gate length by means of a unique sloped etching process (SEP). By extrapolating the results of on-wafer RF measurements through 50 GHz, the researchers obtained a cutoff frequency of 610 GHz and maximum frequency of oscillation of 305 GHz.

Also in that early session, Y.C. Chou and another team of researchers from NGST (Redondo Beach, CA) and the Naval Research Laboratory (NRL, Washington, DC) will offer details on 100-nm InAlSb-InAs HEMT low-noise amplifiers (LNAs) fabricated on 3-in. GaAs substrates. The intent of the LNAs is to fuel phased-array systems applications with extremely low power consumption (2 mW or less). By controlling the wet etch time, the researchers have discovered that they can precisely control the gate recess width, resulting in good RF yield. Their extrapolated current-gain cutoff frequency is better than 200 GHz for devices biased at a drain-source voltage of 0.3 V and a gate-source voltage of -0.3 V. When used in X-band LNAs operating at 0.3-V drain-source voltage and 6.7 mA drain-source current (2 mW power), the associated gain and noise figure at 12 GHz were approximately 12 dB and 3 dB, respectively, with RF yield of better than 80 percent.

In a session on "Quantum, Power, and Compound Semiconductor Devices- Ultra High Speed SiGe and InP-Based HBTs," H. Rucker and colleagues from IHP (Frankfurt, Germany) will unveil their efforts in raising the operating frequencies of SiGe BiCMOS devices. They detail a 130-nm BiCMOS technology with high-speed SiGe:C heterojunction bipolar transistors (HBTs) featuring cutoff frequency of 255 GHz and maximum frequency of oscillation of 315 GHz. They also demonstrate currentmode- logic (CML) ring oscillator gate delays of only 3 ps. The devices were integrated into an HBT module using a BiCMOS technology suitable for millimeter- wave mixed-signal applications such as in 77-GHz automotive electronic systems. The CMOS process features dual gate oxides of 2 and 7 nm for 1.2-V logic and 3.3-V input/output devices, respectively.

In the same session, J.J.T.M. Donkers and associates from NXP Semiconductors (Leuven, Belgium) and IMEC (Leuven, Belgium) will share their efforts on improving the manufacturing process of high-speed devices by developing a novel HBT architecture that is fully self-aligned for maximum reduction of device parasitic elements. The process, which is fully compatible with CMOS, grows the collector and base in a single non-selective epitaxial process step on top of predefined bipolar areas, allowing for collector- base profile engineering. The collector drift region and the extrinsic base are made self-aligned to the emitter by means of a dry etch that removes all polycrystalline material. The remaining epitaxial material defines the intrinsic device within the architecture. With an emitter area of 0.12 X 5 µm², the device achieves cutoff frequency of 300 GHz and maximum frequency of oscillation of 210 GHz.

Also in that session, William Snodgrass and associates from the Department of Electrical and Computer Engineering at the University of Illinois at Urbana- Champaign (Urbana, IL) will detail double heterojunction bipolar transistors (DHBTs) using wide-gap InP collector layers to improve the breakdown voltage and power handling capabilities. By vertically scaling the base and collector epitaxial layers to 20 and 60 nm, respectively, they have fabricated a device with emitter area of 0.5 X 8 µm² with cutoff frequency of 670 GHz and maximum frequency of oscillation of 185 GHz. A device on the same wafer with different dimensions of 0.4 X 4 µm² yielded simultaneous cutoff frequency of 630 GHz and maximum frequency of oscillation of 350 GHz. The researchers also developed a device meant for balanced RF performance, with emitter area of 0.46 X 3.1 µm², which achieved cutoff frequency of 480 GHz and simultaneous maximum frequency of oscillation of 420 GHz.

In the same session, H.G. Liu and associates from the Intitut fur Feldtheorie und Hochstfreqenztechnik (IfH) of the Swiss Federal Institute of Technology (Zurich, Switzerland) will report on DHBTs grown by metal-organic-chemical-vapordeposition (MOCVD) process with a Ga(As,Sb) graded base. The graded base was achieved by ramping the base As/Sb composition ratio from the collector to the emitter side. The end result is a device with cutoff frequency of 603 GHz at room temperature with a breakdown voltage of 4.2 V. The performance of the DHBTs improves with cooling, to reach a cutoff frequency exceeding 700 GHz with breakdown voltage of 3.3 V at 5 K. The maximum frequency oscillation exceeds 110 GHz, the measurement limit of the laboratory’s vector network analyzer (VNA).

C. Monier and colleagues from Northrop-Grumman Space Technology will share their investigations of highspeed DHBT processes for advanced mixed-signal and digital applications. By scaling device geometries, the researchers were able to extend the frequency and bandwidth of experimental devices. Baseline devices have yielded performance levels with cutoff frequencies to 250 GHz and maximum frequencies of oscillation in excess of 340 GHz with maximum current density of 2.5 mA/µm². The investigators have fabricated a large number of circuits with the InP DHBT technology ranging from 50 to more than 4000 transistors, including dividers, amplifiers, demultiplexers, and clock-recovery circuits for applications through 40 Gb/s. They have also assembled a monolithic analog-to-digital converter (ADC) with 6 effective number of bits (ENOB) at analog frequencies to 7.5 GHz and Nyquist performance at a sample rate of 5 GSamples/s. The researchers also developed a 42-b shift register with more than 1000 transistors capable of 35 Gb/s performance.

In a session on "Displays, Sensors, and MEMS-Chemical and Biological Sensors and Microsystems," L. Bandiera and associates from the University of Padova (Padova, Italy) will describe their studies of the interactions of living cells with the silicon chips intended to serve as biosensors for those cells. They researchers developed a new model that includes such features as high-frequency effects (electrochemical nonlinearities with frequency) as well as the cell resting potential, and membrane resistance and capacitance. The investigators stimulated a wide range of cells with a voltage pulse train of constant duration and changing the frequency to study the effects on the cell/electrode impedance interface. Their results have led to the development of an improved model of the impedance of living cells growing in adhesion with electrodes on a singlecell electroporation biochip.

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