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[Devices & ICs]
Optimizing MMICs For Encapsulated Packages
Careful modeling and comparison with measurements can show the effects of a low-cost package on MMIC performance, and help guide the MMIC design for best performance.

Matthew R. Coutant, Charles F. Campbell  |  ED Online ID #17723 |  December 2007

Traditionally, monolithic microwave integrated circuits (MMICs) have been designed for function and performance, but without much forethought for package options. Packages were often developed after the circuit, and this "second-thought" approach would result in loss of circuit performance. A more practical approach is to perform accurate design of high-frequency MMICs for the package itself, in particular, for fully encapsulated packages. By applying a simple electromagnetic (EM) simulation technique, it is possible to account for the encapsulant's effect on the MMIC's field-effect-transistor (FET) active devices. The article that follows will also explore modeling the MMIC's passive structures as well as the package's interconnection transitions. As an example, a 20-GHz commercial amplifier will be used to demonstrate the effectiveness of designing the circuit for the package.

High-frequency packaged products have become more prevalent in microwave systems in recent years. In the past, very few packaged products operating above 6 GHz existed, while today, packaged product offerings are available for many high frequency functions including amplifiers, mixers, filters, voltage-controlled oscillators (VCOs), and multifunction converters. System designers and component suppliers are driving the shift to packaged MMICs. For the system designer, packaged products increase the ease of handling and assembly, and by lowering product costs with known good functions. For the supplier, packaged parts increase the serviceable available market for products, increase the supplier's value-added service and product revenue, and simplify the sales distribution channel by eliminating many difficulties associated with the handling and storage of die products. The challenge for packaged device manufacturers is to design high-frequency products with acceptable RF performance in the lowest-cost package styles available.

Packages are available in many different styles. Lidded soft-board packages and aircavity packages work well at high frequency, but tend to cost more. In contrast, fully encapsulated standard package designs, such as the quad flatpack no-lead (QFN) package that was originally designed for lower-frequency analog and digital applications, are relatively inexpensive. An encapsulated QFN package has a metal paddle (bottom) to which the die is mounted, typically with epoxy. The die bond pads are then wirebonded to metal leads and the entire assembly is covered (encapsulated) with mold compound. Multiple assemblies are built on a lead frame, then singulated as complete individual packages.

The first low-cost packaging attempts put existing high-frequency MMICs, designed for an open-air environment, into encapsulated QFN packages. Examples include amplifiers, analog attenuators, and passive structures. In all instances, the final packaged product generally performs well despite deleterious effects caused by the presence of the encapsulant over the MMIC. Designers must take note of the fact that device gain, power, and linearity performance degrades due to the changes in die operating environment. The operating frequency band can also shift with environmental variations. Consequently, a MMIC designer's challenge is to accurately simulate the performance of the packaged die from the beginning of the process so that the final product will meet the design's performance goals.

As an example, the model TGA2521-SM MMIC from TriQuint Semiconductor (www.triquint.com) is currently being developed as a point-to-point amplifier covering the 17.7-to-19.7-GHz and 21.2-to-23.6- GHz microwave radio bands. The die is being designed with TriQuint's 0.25-µm MMW 3MI pHEMT process and is packaged in a Unisem 4 x 4 16- lead QFN housing (Fig. 1). The special design techniques that account for the encapsulated package environment are detailed.

An important modeling consideration is the transistor performance change that occurs due to die encapsulation. FETs provide transconductance (Gm) with inherent gate-todrain capacitance (Cgd), gate-to-source capacitance (Cgs), and drain-to-source capacitance (Cds). In small-signal models,1-3 these parameters (and others) define the optimum source and drain loads for maximum gain. In nonlinear device models, they define the loads for maximum power and linearity. Traditionally, models are extracted from measurements taken in an open-air (unpackaged) environment. Encapsulant with higher relative permittivity (or dielectric constant, r), in this case r = 4, replaces the air (r = 1) atop the die. The encapsulant raises the FET capacitances by perturbing the fields between the gate, drain and source.

To model the capacitance shifts, a simple procedure using two-and-onehalf- dimensional (2.5D) EM simulations based on Sonnet Software (www.sonnetusa.com) was developed. In the simulator software, the specific FET structure was built with thick lines, gate fingers, drain fingers, and source air-bridges to accurately simulate the FET's physical structure (Fig. 2). The simulation reference planes were set at the same place as the model reference planes. The simulation was then run twice, once in air and once in encapsulant. The resulting S-parameter responses were then fitted to a simplified model, consisting of only the capacitances Cgd, Cgs, and Cds (Fig. 3). The openair capacitances were fit first. For the encapsulant fit, Cgs was fixed to the open air value and Cds and Cgd were refit to the EM simulated S-parameters with encapsulant. Cgs was left unchanged because the extracted value for Cgs is small compared the real intrinsic Cgs value. The absolute delta between the two Cds values and the two Cgd values were then added to the full small-signal or nonlinear model parameters to produce the final encapsulant-shifted version (Fig. 4). This technique was verified by comparing the simulated capacitance shifts to measurements of the FET in air and with encapsulant cured on top. In Fig. 5, the measured capacitance shifts for 12 FETs are compared to the simulated shifts. By using simple EM simulations, the MMIC designer can readily obtain the capacitance shifts caused by encapsulant for many physically different transistors.

In the MMIC, electric fields exist both in the GaAs substrate and in the medium above the die. A microstrip line with length of 200 µm, width of 20 µm, and thickness of 7 µm on 100 µm thick GaAs (r = 12.9) can serve as a good example. In air, the line's characteristic impedance is 70 O with an S21 phase of 13.1 deg. at 20 GHz. In encapsulant, the line's characteristic impedance is 62 O with an S21 phase of 14.3 deg. at 20 GHz. The encapsulant increases the line's phase length and decreases the line's impedance. Encapsulant affects the performance of the MMIC's passive components, including the transmission lines, coupled lines, inductors and capacitors. These components establish the impedances presented to the FETs, thereby helping to define the circuit's gain, return loss, noise, power, and linearity performance. The passive components should be accurately simulated in the correct environment to ensure good circuit performance.

For the TGA2521-SM MMIC amplifier design, all passive components, including microstrip lines, Lange couplers, and capacitors, were simulated by means of the EM simulation software. All components were simulated with 100-µm GaAs substrate with relative dielectric constant (r) of 12.9 and encapsulant with 0.47-mm thickness (r = 4) above the die. At the completion of the design, the simulation consisted of the shifted FET models surrounded by EM simulated S-parameter files.


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