Billions of cellular telephones and their users worldwide are driving demands for faster communications networks. Optical communications systems support long-distance services and serve as the backhaul communications for wireless networks. At one time, optical communications systems operating at 10 Gb/s (OC-192) may have seemed adequate but, with growing voice, data, and video traffic, optical communications networks carrying data rates of 40 Gb/s (OC-768/STM-256) are becoming more commonplace. Beyond that, several companies have already demonstrated components for systems operating to 160 Gb/s.

For example, at the 2007 Optical Fiber Conference, IBM (www.ibm.com) researchers detailed a prototype optical transceiver chipset capable of 160 Gb/s speeds^[1]. The optical transceiver technology is based on CMOS process technology and can be integrated with other optical components fabricated on indium phosphide (InP) and GaAs into a common module that can easily mount onto a high-speed printed-circuit board (PCBs) for use in a wide range of systems and products.

Prior to that, in March 2006, Oki Electric Industry Co., Ltd. (www.oki.com) reported on the successful transmission and reception of 160 Gb/s data over a distance of 635 km. The experiment was part of the “Research and Development on Ultrahigh-speed Backbone Photonic Network Technologies” project consigned by Japan’s National Institute of Information and Communications Technology (NICT). The data transmission included high-speed video.

For all of these high-speed networks, the system clock is one of the more critical components, and Phase Matrix (San Jose, CA) is addressing that need with high-performance, low-jitter clock modules suitable for long-haul telecommunications as well as test-and-measurement applications. Models are available in coaxial single-ended versions with sine-wave outputs from 39.813 to 43.018 GHz as well as in compact surface-mount housings with differentialoutput sine wave signals at 39.813 and 43.018 GHz.

The coaxial 40-Gb/s clock oscillator, model HSC-41415-08K, provides single-ended sine-wave output signals from 39.81 to 43.01 GHz controlled by a tuning voltages of 0 to 12 V with tuning sensitivity ranging from 300 to 600 MHz/V. Output signals are at +5 dBm or more, available at a K connector. Ideal for OC-768/ STM-256 applications, the low-jitter clock oscillator features a fast slew rate of 25 V/ns or better, 50-percent typical duty cycle, and minimum modulation bandwidth of 20 MHz.

Model HSC-41415-08K consists of a 10-GHz low-noise silicon-bipolar transistor oscillator with tuning by means of a hyper-abrupt silicon varactor diode. The silicon bipolar transistor features a maximum frequency of oscillation (f_max) of 40 GHz and maximum available gain of 16 dB at 4 GHz. The device features a common-collector configuration and uses 40 emitters with emitter width of 0.5µm and 2-µm emitter-toemitter width. The oscillators feature a planar microstrip resonator with optimized quality factor (Q) for low noise at 10 GHz.

The varactor diode provides enough tuning range to compensate for aging effects or frequency variations due to temperature. Within model HSC-41415-08K’s package, 10-GHz signals are multiplied to 40 GHz by means of a GaAs pseudomorphic-highelectron- mobility-transistor (PHEMT) frequency multiplier. The outputs of the multiplier are boosted and buffered by means of a low-noise GaAs FET monolithic-microwave-integratedcircuit (MMIC) amplifier. Prior to the output connector, signals are passed through a bandpass filter to minimize harmonic and subharmonic feedthrough signals.

The approach results in phase noise of typically -90 dBc/Hz offset 100 kHz from the carrier and -130 dBc/ Hz or better 10 MHz from the carrier. Second and third harmonics are controlled to typically -30 dBc while nonharmonic spurious levels are typically -30 dBc.

Phase noise, of course, is commonly used to characterize oscillator quality in analog or frequency-domain systems. But in digital or time-domain scenarios, the closely related parameter jitter is often used. Jitter can be defined as the unwanted variations in timing over some portion of a period waveform with respect to a jitter-free reference. It can be specified in terms of phase units, such as radians, time units, such as seconds, or unit intervals (UIs). Because jitter is difficult to measure directly, especially at rates as high as 40 Gb/s, it is often calculated from measurements of integrated phase noise performed with a phase-noise test system for a given expanse of fixed offset bandwidths, such as 50 kHz to 80 MHz for OC-768 systems.

Phase noise at offset frequencies close to the carrier plays a much larger role in the effects of the integrated phase noise (jitter). Phase noise at frequencies far from the carrier (10 MHz and greater) has little effect on jitter, whereas phase noise close to the carrier (50 kHz to 1 MHz) has significant effects on jitter performance. For the model HSC-41415-08K clock oscillator, the maximum jitter is only 200 fs for offsets from 50 kHz to 80 MHz. (For those seeking to better understand jitter, Phase Matrix offers a phase-noise-to-jitter conversion tool at its web site, at http://www.phasematrix.com/design_tools/Jitter.html).

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