Minglin Ma and Chunhua Wang

Quadrature oscillator designs are often fraught with challenges because of the coupling required. A quadrature oscillator can be formed with a pair of oscillators operating in quadrature, but these circuits must be properly coupled with minimal loss and noise. Fortunately, a method has been developed to use two identical folded-type complementary negative-resistance inductive-capacitive (LC) oscillators linked by means of a pair of superharmonic coupling capacitors. The two oscillators' PMOS and NMOS cross-coupled transistor pairs are separately biased in current mode and coupled by the capacitors. Once fabricated in an 0.18-m CMOS process, the oscillator feature outstanding phase-noise performance.

Quadrature oscillators are often needed as local oscillators (LOs) in transceivers with low-intermediate-frequency (low-IF) or zero-IF architectures.1 Several techniques are available for generating these quadrature signals, including the use of a divide-by-two frequency divider followed by a voltage-controlled oscillator (VCO) running at the doubled frequency. Unfortunately, this approach requires a stable 50%-duty-cycle VCO. Another technique is the use of a VCO followed by a passive resistive-capacitive (RC) filter, although a power-consuming buffer stage is needed between the VCO and the filter.2 As a third option, two

VCOs can be run in quadrature by coupling the two sources.3-5 Coupling can be achieved by a number of different complementary devices: transistors, inductors, or capacitors. Transistor coupling suffers from a tradeoff between quadrature accuracy and phase noise. Moreover, the use of coupling transistors increases the power consumption. Inductors used for coupling are usually too large for an integrated circuit (IC). By selecting the third option, based on superharmonic capacitive coupling (Fig. 1), no extra noise is added and no extra power consumption is required for coupling. This type of coupling capacitor is easily implemented in an RF IC process while still maintaining small die area. To minimize the supply voltage, the coupled oscillators feature a folded design (Fig. 1). The PMOS and NMOS cross-coupled transistor pairs in the folded complementary negative-resistance LC oscillator reported here are biased in current mode. Compared to a negative resistor LC oscillator biased in voltage mode, the oscillator has low phase noise.

A negative-resistance LC oscillator biased in voltage mode is shown in Fig. 2(a). In this kind of oscillator, the gate-to-drain voltage, Vgd, is equal to the negative differential output voltage of the LC tank, Vout. When Vout is equal to zero, the two NMOS transistors operate in the saturation region and the NMOS cross-coupled transistor pair acts as a negative resistor to replace the energy loss of the resonant circuit. When Vout is greater than the threshold voltage, Vt, the gate-drain voltage, Vgd, of one transistor is higher than Vt and operates in the device's triode region. Voltage Vgd for the other transistor decreases, so that the transistor operates in the saturation region. The transistor in the triode region acts like a resistor, which will lead to additional loss, which can significantly degrade oscillator phase noise.

A negative resistor LC oscillator biased in current mode is shown in Fig. 2(b). There is a current source between the common source point and ground. When Vout is equal to zero, the two NMOS transistors work in the saturation region and the NMOS cross-coupled pair acts as a negative resistor to replace the energy loss of the resonant circuit. Using appropriate size devices, it is possible to ensure that the overdrive voltage is smaller than Vt. When Vout is greater than Vt, one transistor works in the triode region, and the other transistor is switched off. The current of the transistor working in the triode region remains unchanged, so it will not add additional loss to the LC tank.

The folded-type complementary negative resistor LC oscillators that are the basis of this work are biased in current mode with low phase noise Fig. 3(a)>. The proposed quadrature oscillator (Fig. 1) consists of two identical folded-type complementary negative resistor LC oscillators and two superharmonic coupling capacitors. A conventional complementary negative-resistor LC oscillator is shown in Fig. 3(b) for comparison.

Many recent publications have shown that the complementary cross-coupled structure in Fig. 3(b) is suitable for lowphase- noise oscillators.6,7 The complementary cross-coupled oscillator achieves low noise by merit of its symmetric rise and fall transients and good suppression of upconverted 1/f noise. This structure uses both NMOS and PMOS cross-coupled amplifiers to provide the negative resistance necessary to compensate for losses in the LC tank. The main drawback of this topology is the need for a relatively high supply voltage.

The inductances shown as Lbond1,2 in the foldedtype complementary negative resistor LC oscillator are bond wires. They provide a DC path for the two crosscoupled pairs and present a high impedance to AC signals. Capacitors C1,2 have been added between the cross-coupled PMOS and NMOS amplifiers to decouple the DC bias without affecting the AC signal paths. These capacitors appear as short circuits at very high frequencies. This oscillator design can operate from a low voltage supply while preserving the characteristics of the conventional complimentary structure shown in Fig. 3(b). Figure 4 shows the waveforms of the output voltages of the circuit in Fig. 3(a), while Fig. 5 shows the common source voltages of the circuit in Fig. 3(a). Assuming that voltage VA is increasing from time t1 to time t2, transistors M1 and M3 work in the triode region, and transistors M2 and M4 are switched off, so that:

VY = VB VGS3 (1)

VX = VC + VGS1 (2)

IM1 = I1 (3)

IM3 = I2 (4)

During this time, currents IM1and IM3 do not change, so voltages Vgs1 and VGS3 remain constant. This implies VGS1 voltage VY follows VB and VX tracks VC. From time t2 to t3, the common-source signal clamps the output amplitude at high bias currents and the oscillator enters the voltage-limited regime, This clamping occurs since the transistor drain voltage can not be lower than the source voltage, as this would reverse the current flow. From time t3 to t4, voltage VY follows VB and VX follows VVCC.

As is evident from the simulated waveforms in Fig. 6, the transistor commonsource voltages (VX and VY) oscillate at 20 with an antiphase relationship, while the transistors' output voltages (VA-D) oscillates at 0.

It is clear that the common-source voltages follow the output voltages. An anti-phase relationship has been formed between the second-order harmonics, VY and VZ. This means that there is a time delay, T/4 (where T is the oscillation period), between the second-order harmonics, and there is a time delay between the output of the two coupled folded-type complementary negative-resistance LC oscillators. In principle, the two differential oscillators should oscillate in quadrature.

From Fig. 6, it is apparent that there is an anti-phase relationship between VX and VY. Therefore, it is possible to couple VX and VZ together and VY and VW together to achieve a quadrature output. Figure 7 shows simulated waveforms for these quadrature output voltages.

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Table 1 lists the inductor values for the quadrature oscillator, where the quality factor (Q) is usually the dominant parameter for these components. For the folded complementary negative resistor LC oscillator circuit shown in Fig. 1:

L1+L2=L3 = L4 = 3.93 nH (5)

QL= 8 (6)

For an LC oscillator, oscillation frequency f0 is given by:

f0=1/tankCtank)0.5> (7)

For a LC oscillator, the oscillation frequency (f0) is given by Eq. 8, where

Ltank = (L1 + L2) || (L3 + L4) = 3.93 nH (8)

Ctank = 1/tank(2πf0)>2 = 1.19 pF (9)

Ctank = Cdg1 + Cgs1 + Cdg2 + Cgs2 + Cdg3 + Cgs3 + Cdg4 + Cgs4 (10)

where

Cdg1-4 = the drain-gate capacitances of transistors M1, M2, M3, and M4 and Cdg1-4 = the respective gate-source capacitances of transistors M1, M2, M3, and M4, with

RL1 = 2πf0L/QL (11)

Rtank (QL2RL1 + QL2RL2) || (QL2RL3 + QL-2RL4) QL2RL1 (12)

Ibias ItankVmax/Rtank (13)

To ensure oscillation startup, the total transcondeuctance must be chosen to satisfy the conditions of Eq. 14:

g1,2 + g3,4 = 2/Rtank (14)

where g1,2 and g3,4 are the transconductances of the cross-coupled M1-2 and M3-4 pairs, respectively.

For M1-4 in the saturation region:

ID = 0.5nCox(W/L)(VGS VTH)2 (15)

g = ?ID/?VGS = nCox(W/L) (VGSVTH)=K(W/L)(VGSVTH) (16)

g = DK(W/L)>0.5 = bias>0.5 (17)

W = (gm2L)/(2KIbias) (18)

For symmetrical complementary design:

WPMOS = 2.8WNMOS (19)

The circuit parameter values have been shown in Table 2. The quadrature oscillator has been fabricated in a chartered 0.18-m CMOS process, with a picture of the fabricated oscillator shown in Fig. 8. Figure 9 shows the measured phase noise, with performance of -94.14 dBc/Hz offset 100 kHz from the carrier and -122.91 dBc/Hz offset 1 MHz from the carrier. The measured quadrature output is shown in Fig.10. Symmetry is preserved throughout the layout. All DC and control signals are bond wired to the package, with standard ground-signal-ground pads are used for on-chip probing the RF output. The layout was done according to RF design guidelines, keeping DC traces thin and AC connections wide and as short as possible.

Table 3 outlines the performance of this design and lists the performance of the previous published quadrature oscillators. The figure of merit (FOM) is introduced in ref. 8 and explained in Eq. 20: FOM = L(ΔΩ) 20log(Ω0/Δ) + 10log(PDC/1 mW) (20)

where

L(ΔΩ) = phase noise at offset of ΔΩ and PDC = the power dissipated in the oscillator (in mW).

From Table 3, it can be seen that compared to ref. 3, the folded-type oscillator operates at a lower supply voltage. Without coupling transistors, the power consumption is much less.

Acknowledgment

The authors would like to thank the National Natural Science Foundation of China for financially supporting this research under grant No. 60776021.

References

1. M. S. J. Steyaert et al., "Low-voltage low-power CMOS-RF transceiver design," IEEE Transactions on Microwave Theory and Techniques, Vol 50, No. 1, 2002, pp. 281-287.

2. J. Crois and M. Steyaert, "A fully integrated 900 MHz CMOS double quadrature downconverter," in 42nd IEEE International Solid-State Circuits Conference (ISSCC), 1995, Technical Digest.

3. M. Minglin, W. Chunhua, and Y. Changyong, "2.4 GHz Quadrature Differential LC Oscillator Using Two Coupling Capacitors," FREQUENZ, Vol. 63, 2009, pp. 20-23.

4. S. L. J. Gierkink et al., "A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling," IEEE Journal of Solid-State Circuits, Vol. 38, No. 7, 2003, pp. 1148-1154.

5. O. Frioui et al., "A very low phase noise fully integrated CMOS quadrature LC oscillator for 2.4 GHz bluetooth/WLAN applications," in 2007 International Symposium on Communications and Information Technologies (ISCIT).

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8. R. Poore, "Accurate simulation of mixer noise and oscillator phase noise in large RFICs," 1997 Asia- Pacific Microwave Conference Proceedings.