Figure 2 shows the input resistance of a cross-coupled transconductor (devices M3 and M4) and its equivalent circuit. The following equations are based on the equivalent circuit:

vin = vgs4 - vgs3   (1)

iin = gm3 vgs3 = gm4 vgs4   (2)

According to Eqs. 1 and 2, the equivalent negative resistance, rin,n, can be derived by Eq. 3:

rin,n = vin/ iin = 1/gm3 - 1/gm4   (3)

where:

gm3 = the transconductance of M3 and

gm4 = the transconductance of M4.

Assuming that gm3 = gm4 = gmn, then

rin,n = vin/ iin = -2/gmn   (4)

In the same way, it is easy to get rin,p, the negative resistance of devices M1 and M2:

rin,p = vin/iin= -2/gmp   (5)

The total LC tank parallel negative resistance is

rtotal = -2/( gmn + gmp)   (6)

For startup, the total negative resistance exhibited by the transconductances M1-M2 and M3-M4 must be less than the parallel parasitic resistance of the LC resonator—namely, Eq. 7:

rtotal = 2/(gmn + gmp) < rp   (7)

where:

rp = the LC parallel resonant circuit equivalent resistance.

As Fig. 3 depicts, for deep-submicrometer MOSFETs, the threshold voltage is no longer constant. Nevertheless, it can be manipulated by the DC bias at the body terminal, adding one more degree of freedom to circuit designs. Typically, the threshold voltage of an n-channel MOSFET is given as19:

Vt = Vt0 + γ[(2ΦF + VSB)0.5 -(2ΦF)0.5]   (8)

where:

Vt0 = the threshold voltage for VSB = 0;

VSB = the source-to-body voltage;

ΦF = a semiconductor parameter with typical value in the range of 0.3 to 0.4 V; and

γ = a process-dependent parameter.

To suppress the negative influence from body transconductance, capacitor Cb is inserted between the source terminals and body terminal. The current-limiting resistor, Rb, is included at the body terminal to prevent excessive junction conduction.

According to Eq. 8, if the value of VSB has changed, the threshold voltage will also change, as the source terminal of the NMOS device is connected to inductor L2 and voltage VS is almost close to 0 V. The value of threshold voltage Vt can be changed by adding different body-bias voltage, Vb. At the same time, as the drain current associated with the value of VGS - Vt, namely ID, is controlled by the voltage difference of VGS - Vt, while Vt changes with the change of Vb, the value of Vg is adjusted according to the change in threshold voltage to maintain current ID at a constant value.

In this way, this novel topology can operate with very low power consumption. Figure 4 shows simulated effective threshold voltage and Vb. These simulated results show that once the FBB voltage Vb increases by 100 mV, the threshold voltage will decrease by almost 19 mV.

Tunable oscillator operation is vital to many modern applications. In the current VCO design, the VCO gain parameter, KVCO, determines the VCO’s phase-noise performance and loop characteristics of a PLL circuit. For low phase noise, it is usually desirable to have a value of KVCO as low as possible, although a small value of KVCO also means a narrow frequency tuning range. To extend the frequency tuning range for a design with small value of KVCO,  a switched capacitor array is used in the current design (Fig. 5).

The switched capacitor array is implemented with nMOS devices since the 1/f noise models for nMOS devices were found to be more accurate than those for pMOS models. The aspect ratio of the switching transistors should be as large as possible so that they operate mostly in the triode region where the noise characteristics are lower, but not so large that their parasitic capacitances limit the tuning capability of the VCO.