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In typical implementations, a synthesizer would use a feedback divider to control the frequency produced by the oscillator. The feedback divider’s output noise exhibits the same lowpass transfer characteristics [B(s)] as the input noise, with the divider’s close-in noise of greater importance than its noise level. Such a divider is built with logic gates, using typical technologies as TTL, CMOS/BiCMOS, and ECL, but rarely as a regenerative divider based on frequency mixers. TTL dividers can achieve low noise levels28, to -170 dBc/Hz, with good close-in noise, but their maximum clock frequency rarely exceeds 150 MHz.

Reducing the reference frequency from 100 MHz to 10 MHz would result in degradation of output phase noise of 20 dB, making the TTL divider unsuitable for locking with 100-MHz signals. CMOS/BiCMOS dividers can achieve similar noise levels at offsets greater than 10 MHz, but with more flicker in higher close-in noise levels that makes them poor choices for low-noise synthesizers. A better choice would be using ECL dividers, which typically exhibit noise levels of -155 dBc/Hz.

Direct frequency synthesis can achieve lower noise than when using feedback dividers and phase-detector combinations. Direct synthesis employs harmonic multipliers, based on step-recovery, PIN, or Schottky diodes, to generate higher-frequency signals. Such diodes allow multiplication of the 100-MHz signal from an OCXO with minimal degradation in noise, with an equivalent noise floor of about -174 dBc/Hz. The synthesis approach can achieve a slightly better noise performance when using references having power levels considerably higher than 0 dBm. The drawback of this method is the high far-offset output noise, with 20logN degradation.

Improved noise performance can be achieved by combining the direct frequency synthesis approach with a PLL method. A high-frequency phase detector is used to lock the oscillator to the harmonic of the reference clock produced by diode harmonic multipliers. By using a low-noise OCXO with a low-noise high-frequency oscillator, such as a DRO or SAW oscillator, this hybrid method is capable of achieving excellent noise levels. Close-in performance is determined by the OCXO and harmonic multiplier, while far-offset performance is determined by the high-frequency oscillator.

Searching For Low-Phase-Noise Synthesizers, Fig. 5

The KFSULN1024-100 DRO reference synthesizer is an implementation of such an approach, providing a 10.24-GHz output signal with low noise. The design locks a 10.24-GHz DRO from Synergy Microwave Corp. to the harmonics of an internal OCXO reference, using a low-noise PLL with double-balanced mixer serving as phase detector. By using frequency multiplication from the reference, the noise performance required from the mixer and loop filter is relaxed by about 40 dB. The design employs low-noise operational amplifiers to achieve low noise levels.

Searching For Low-Phase-Noise Synthesizers, Fig. 6

The synthesizer was characterized with a model FSUP signal source analyzer from Rohde & Schwarz. The synthesizer and test system were both placed inside a Faraday cage to minimize the effects of outside noise sources. Figure 5 shows the test system, while Fig. 6 shows the test results.

The synthesizer produces a +10 dBm signal at 10.24 GHz. The low-noise internal OCXO determines the synthesizer’s performance for offset frequencies between 10 Hz and 1 kHz, with -70 dBc/Hz phase noise at 10 Hz offset and -121 dBc/Hz at 1 kHz offset. Low-noise synthesis techniques produce a low noise floor of -138 dBc at 10 kHz offset. Above 1 MHz, the noise floor is determined by the DRO and reaches -168 dBc/Hz.

Prof.-Dr.-Ing.-habil Ulrich Rohde, Chairman*

Dr. Ing. Ajay Kumar Poddar, Chief Scientist

Dorin Calbaza, Senior Design Engineer

Synergy Microwave Corp., 201 McLean Blvd., Paterson, NY 07504; (973) 881-8800, FAX: (973) 881-8361.

*Ulrich Rohde is also affiliated with Cottbus University, Brandenburg, Germany.

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