From Eq. 4, it can be seen that as VC changes, Vgs will change, then resistance rds will also change. Therefore, the feedback resistance is variable, as is the gain.

Variable-Gain LNA Reaches 26 GHz, Fig. 4

Variable-Gain LNA Reaches 26 GHz, Fig. 5

Figure 4 shows a complete schematic diagram of the 26-GHz CMOS VG-LNA. The preamplifier is comprised of a T-section matching network and a resistive-feedback current-reuse stage. Based on the methodology in ref. 10, simultaneously input impedance and noise matching at a frequency of 26 GHz was achieved by selecting appropriate values for the passive circuit elements C1, C2, and L1 and the size and bias of the input resistive-feedback current-reuse network. Figure 5 provides a small-signal equivalent circuit of the preamplifier. From Fig. 5, the input impedance of the small-signal equivalent circuit is given by11:

Zin = 1/sC1 || 1/sC2 + sL1 + Zin1             (5)

where:

Zin1 = 1/[Zd/( Zd + RF)] x [(gmN + gmP) + s(CgsN + CgsP)]              (6)

and

Zd = the input impedance of the post-amplifier.

To achieve sufficient gain, the post-amplifier is comprised of three cascaded common-source stages and an output matching network. In the first stage, proper scaling of the transistor and gate inductance are used to shift optimum source impedance, Zopt, to 50 Ω, which makes it easier to achieve low noise figure. The output of each stage is loaded with a bandpass (or a highpass) combination of L and C to provide parallel resonance and to increase gain at the 26-GHz center frequency. Inductor L6, which is connected to the source of transistor M3, improves the stability of the LNA. The DC block, about 60 fF at the output, was chosen for output matching. Since this small capacitance might be sensitive to process variations, it has been composed of two MIM capacitors in series so as to desensitize the output matching from processing variation. The component parameters are as follows:

L1 = 414.8 pH;  

L2 = 1 pH;

L3 = 327.4 pH;

L4 = 96.7 pH;

L5 = 260.7 pH;

L6 = 114.6 pH;

C1 = 7.6 pF;

C2 = 273.65 pF;

C3 = 4 pF;

C4 = 70 fF;

C5 = 10 pF;

C6 = 60 fF;

R1 = kΩ;

R2 = kΩ; and

R3 = kΩ.

The bias conditions are Vdd = +1 VDC and Vgg = +0.7 VDC. The CMOS transistors used in these circuits have been demonstrated to have cutoff frequency, ft, of around 50 GHz and maximum frequency of oscillation, fmax, of around 90 GHz. The excellent ft and fmax performance levels mean that it should be possible to use this CMOS process for high-performance K-band LNAs.

Variable-Gain LNA Reaches 26 GHz, Fig. 6

Variable-Gain LNA Reaches 26 GHz, Fig. 7