For measurement purposes, a 50-GHz signal source was used to provide sufficient input power to saturate the doubler and quadrupler. Both components were both measured using wideband 50-75-GHz and 75-110-GHz power sensors. The output components included a coaxial RF probe, a waveguide transition, and a WR-10 waveguide attenuator and power sensor. The output component losses were measured using a VectorStar vector network analyzer (VNA) from Anritsu Co. with 110-GHz range.

Fundamental leakage to the power meter head was negligible, as the 75-GHz waveguide used for the attenuator and power sensor had a cutoff frequency of 60 GHz. The third- and higher-harmonic content of the doubler was believed to be negligible because of the lack of gain in the output amplifier at greater than 1.5 times the input frequency.

The doubler was used as a driver to achieve sufficient power to drive the PA into saturation. The doubler and PA were epoxied side by side on a metal block and RF/microwave connections made by means of bond wires. A three-dimensional (3D) EM simulation was used to model bond-wire losses at each measurement frequency. The specific doubler used for this test was characterized separately and the measured output power level, corrected for bond-wire loss, was used to calculate the PAE.

Design An ETSI E-Band Circuit, Fig.1

Figure 1 shows the measured and simulated results for the doubler. With a 4-V supply, the doubler provides output power above +15 dBm from 70 to 88 GHz. The PAE exceeds 4% over this same frequency band. The fundamental rejection was not measured, since the doubler’s Q-band range falls below the cutoff frequency of the waveguide used in the measurement setup.

Design An ETSI E-Band Circuit, Fig.2

Figure 2 shows the measured output power and PAE results for the quadrupler with a +4-VDC supply, along with its simulated performance. The quadrupler offers maximum output power of +19.2 dBm at 85 GHz and delivers more than +18 dBm output power from 76 to 89 GHz. The quadrupler’s PAE exceeds 6% over this same bandwidth.

Design An ETSI E-Band Circuit, Fig.3

Figure 3 plots measured S-parameters for the PA, while Fig. 5 shows the PA’s measured saturated output power and PAE as functions of frequency for drain-source voltages (VDS) of +3 to +5 VDC. At the higher drain potential, the saturated output power reaches as high as +24.2 dBm (265 mW) and at least +23 dBm (0.2 W) from 71 to 86 GHz. For a +4-VDC drain potential, the PAE exceeds 8% from 71 to 86 GHz.

To accurately gauge the impact of packaging on the PA, a 3D EM simulator was used to calculate the impact of the bond wires on amplifier performance, and that simulation data was then integrated into the Microwave Office simulations. The full chip was developed as a computer model with the aid of AWR’s Analyst™ 3D EM analysis software, which uses the finite-element method (FEM) of analysis. These simulated results, shown in Fig. 4, compare favorably with measured data. Variations between the simulations and measurements can actually be traced to the semiconductor wafers themselves, which have nominal thickness of 50 μm for this process. The measured wafers were close to the edge of the process window, a major factor for the shift in performance between simulations and measurements.

Design An ETSI E-Band Circuit, Fig.4