By using a low-cost SPICE-based simulator, this innovative cascode amplifier achieves broadband, low-noise performance through 12 GHz using an integral differential error amplifier.
Broadband amplification usually employs a tradeoff in noise performance. But this amplifier design features a cascode configuration using high-frequency GaAs field-effect transistors (FETs) and a silicon-bipolarbased differential error amplifier to reduce the effects of 1/f device noise while preserving fast transient response. The amplifier maintains flat gain from 1 kHz to 10 GHz, with a 12 GHz bandwidth, while achieving an impressive risetime of 23.9 ps.
Cascode amplifiers essentially use two stages, with one a transconductance amplifier followed by a current buffer amplifier. In contrast to single-stage designs, this configuration can provide better input/output isolation and greater bandwidth for a given device type. The cascode can be formed of various transistor types, including silicon bipolar junction transistors and GaAs field-effect transistors (FETs), with one of the devices working as a common emitter or common source and the other as a common base or common gate. By eliminating direct coupling from output to input by means of the buffer stage, a cascode design provides high isolation between ports.
This DC-to-12-GHz cascode amplifier (Fig. 1) is based on a pair of NE325S01 low-noise N-channel GaAs heterojunction FETs in the gain portion of the circuit and a pair of NE68539 NPN silicon bipolar transistors with high cutoff frequency (12 GHz) in the transconductance error amplifier; both devices are from NEC and available from California Eastern Laboratories.
In the broadband amplifier circuitry, an input signal to the gain stage appears as a common-mode signal to the error amplifier. The error signal taken from the source of the first FET in the cascode appears as a differential signal. This error signal consists of 1/f noise as well as harmonic distortion. By summing the error signal current into the source of the second FET in the cascode, the 1/f noise and harmonic content can be reduced by 20 to 30 dB at the output of the amplifier.
Taking a closer look at the circuitry of Fig. 1, the input divider consists of resistors RDIV1 and RDIV2, which attenuate the input signals and provide a 50-O input match, with the sum of the two resistors, RDIV1 + RDIV2, equal to 50 O and the ratio, RDIV2/(RDIV1 + RDIV2), selected to yield a signal at the base of transistor X14 equal to the low-frequency signal at the base of transistor X15. Thus, the input signal is seen as a common-mode signal to the error amplifier, producing little or no signal current into the collector of transistor X14. The major components of the error signal consist of 1/f noise and harmonic distortion from the gain cell. The signal current produced as a result of the error signal, which appears at the output of X13 can be found from the ratio of the error signal to source resistor RSOURCE: (error signal)/(RSOURCE). The signal current produced by the error amplifier is simply the product of the error signal and the transconductance (gm) of the error amplifier. The transconductance is set by the standing current of the differential device pair forming the error amplifier. VGAIN is adjusted for minimum levels of 1/f noise at the output of the amplifier.
The input impedance at the base of error-amplifier transistor X14 is high given the input signal is seen as a common-mode signal to the error amplifier, given both bases of the error amplifier have the same input signal. The standing current in the error amplifier is set low relative to the standing current of the gain cell to lower the 1/f noise of the error amplifier relative to the 1/f noise of the gain cell. The 1/f noise corner of the bipolar transistors is much less than the 1/f noise corner of the N-channel heterojunction FETs. These factors cause the 1/f noise of X13 to be the dominant noise source of the amplifier at low frequencies.
In analyzing the signal flow through the broadband amplifier, the source of the first FET of the cascode is the second input to the error amplifier. The sum of RDIV1 and RDIV2 is the input resistance of the amplifier. The quotient, RLOAD/RSOURCE to the first order sets the gain of the cascode, where RLOAD is the output resistance of the amplifier and RSOURCE is the source resistance of the amplifier. The value of voltage supply VGAIN sets the gain of the error amplifier by controlling the standing current of the differential pair.
The two FETs of the main gain amplifier are labeled X13 and X16. These are three-terminal devices, each with a gate, drain, and source. Both are N-channel heterojunction FETs manufactured by California Eastern Laboratories as model NE325SO1. The other two transistors in the schematic diagram, X14 and X15, form the transconductance error amplifier. Both are also threeterminal devices, but with base, collector, and emitter. Both are NPN silicon bipolar transistors manufactured at California Eastern Laboratories as model number NE68539.
The gate of transistor X13 serves as the input port for the amplifier. The drain of transistor X16 serves as the output port of the amplifier. The performance of the novel amplifier design was simulated using the TopSPICE simulation program from Penzar Development. TopSPICE is an affordable circuit simulator based on SPICE for use on computers with 32 or 64-b Windows operating systems. It can handle simulations on designs from the transistor to the system level, performing mixed-mode, mixed-signal analysis on designs consisting of combinations of analog and digital circuits and behavioral blocks.
Figure 1 is a plot of simulated frequency response for the amplifier design The plot shows gain of 12.2 dB at 1 kHz, dropping to 12 dB at 2 GHz. The gain is flat within 0.24 dB from 1 kHz to 2 GHz. The gain drops by 3.1 dB at 12.3 GHz, for an approximate 3-dB bandwidth of 12.3 GHz.
Figure 2 shows simulated transient response: excellent performance with no overshoot and risetime of 23.9 ps.
Figure 3 is a plot of simulated noise figure versus frequency. The noise figure is 9.3 dB at 10 Hz where the 1/f noise is dominant. The noise figure drops to 5.3 dB at 100 Hz, 3.8 dB at 1 kHz, and 3.5 dB at 10 kHz.
Figure 4 is a plot of simulated output noise as a function of frequency. The two plots are shown in scales of decibels (dB) and root-meansquare (RMS) voltage per (Hz)0.5 of bandwidth. At 10 Hz, the output noise is -151.2 dB or 27.4 nVRMS/ (Hz)0.5. At 100 Hz, the output noise is 159.2 dB or 11.0 nVRMS/(Hz)0.5. At 1 kHz, the output noise is 162.5 dB or 7.5 nVRMS/(Hz)0.5. At 10 kHz, the output noise is 163.1 dB or 7.0 nVRMS/(Hz)0.5.
Figure 5 shows the transfer characteristics of the amplifier, using a 1-kHz input signal to generate a simulated FFT of the amplifier's output signal. The input signal has an amplitude of 6.9 dB. The second- harmonic distortion at the output is down 95.4 dB from the fundamental.
Figure 6 shows a simulation of the second-harmonic distortion as a function of input frequency from 1 kHz to 1 GHz. The simulated performance shows the break point to be at 10 MHz, where the output distortion begins a steep rise. The output distortion for a 1-kHz input signal is 95.4 dB, while the output distortion for a 10- MHz input signal is 84.6 dB. At higher frequencies, the distortion continues to rise, with the output distortion for a 100-MHz input signal being 64.5 dB and the output distortion for a 1-GHz input signal being 55.9 dB.