This amplifier delivers 490 W power from 1200 to 1400 MHz with high efficiency by optimizing impedance terminations at fundamental and harmonic frequencies.
Pulsed radar systems require high power levels but, increasingly, also demand power amplifiers with high efficiency. To meet those needs at L-band frequencies from 1200 to 1400 MHz, a Class F amplifier was developed with reduced conduction angle to maximize efficiency. The amplifier employs four parallel, internally matched silicon-bipolar transistors in a common-base configuration. They are biased in Class C mode to achieve the high output power levels required by pulsed radar systems. Operating with 150-s pulses at a duty factor of 10 percent, the amplifier achieves more than 490 W peak output power from 1200 to 1400 MHz with minimum efficiency of 57 percent.
The high gain of a common-base configuration compared to a common-emitter configuration using silicon bipolar junction transistors (BJTs) makes it more suitable for high-frequency power amplifiers in radar systems.1 As an example, common-base silicon bipolar Class C amplifiers are commonly used in L- and S-band radar applications where system output-power requirements are typically in the multiple-kilowatt range. In such applications, a 1- or 2-kW module is usually designed as the basic building block, with several modules combined to achieve the required output-power level.
Because of a trend for increasing energy density in more compact radar systems, the amplifiers in these systems must be as efficient as possible to accommodate tight
space requirements that must also include power supplies and heat-sinking structures. The amplifiers should be stable and rugged in order to preserve the integrity of amplified pulsed signals under load mismatch conditions.2
A Class C bias configuration is commonly used to improve the efficiency of pulsed radar bipolar-transistor amplifiers. The efficiency of a conventional Class C amplifier can be further enhanced by the use of higher-order harmonic tuning to minimize power dissipation across the active device at harmonic frequencies. This is the so-called Class F amplifier bias configuration, using a reduced conduction angle.3 Conventional Class F power amplifiers use multiple-resonator output filters to control the harmonic content of their collector-voltage and/or collector-current waveforms (Fig. 1). Flattening of the waveforms by controlling the harmonics allows the majority of the collector current to flow when the collector voltage is low, thus reducing power dissipation due to harmonic signal energy.
For a Class F power amplifier where the active device is biased under Class B conditions (with conduction angle equal to p), the one-half sine-wave current waveform contains only even harmonics. In this case, odd harmonics can be used to flatten the voltage waveform during the time of conduction. As stated in ref. 3, biasing the active device under Class C conditions (with conduction angle less than p) causes all harmonics to be present. A given harmonic can be nulled at a specific conduction angle, but most of the other harmonic frequencies will remain. Consequently, flattening the voltage waveform must be accomplished by the addition of a single harmonic.
When designing an RF power amplifier, it is not practical to terminate an infinite number of harmonics since this can be extremely challenging and time consuming in a broadband design. Furthermore, the magnitude of higher-order harmonics is negligible for devices with low maximum frequency of oscillation, fmax (like those used in this work), and only second and third harmonics can be used for wave shaping. As shown in ref. 4, most of the increase in efficiency due to wave shaping can be obtained with only the first few harmonics correctly terminated.
The design of an RF transistor represents a compromise among various performance parameters, including power, gain, and efficiency, yet still provides robust operation into an output impedance mismatch with high breakdown voltage and good long-term reliability. The negative-positive-negative (NPN) silicon BJT used in the power amplifier was designed and fabricated at M/A COM Technology Solutions (Torrance, CA). The device has an interdigitated geometry with very tight emitter-to-emitter pitch to enhance the ratio of the emitter periphery to the base area. Double-layer gold metallization is used to lower the output capacitance while also providing excellent mean-time-to-failure (MTTF) at L-band frequencies.
Diffused silicon emitter ballast resistors were used for better current sharing within the transistor die itself. For the amplifier, four paralleled and internally matched transistors were combined to achieve the required output power (Fig. 2). The transistors are attached to a 40-mil-thick metallized beryllium oxide (BeO) substrate over a 60-mil-thick copper-tungsten (CuW) flange.
For an amplifier designed with packaged transistors, matching networks can be implemented using completely external circuitry, but parasitic elements from the packages can severely limit the useful bandwidth of high-power RF devices. This bandwidth limitation was partially overcome by including part of the device's input and output matching networks inside the package. The packaged transistors used in this work are internally matched with input and output metal-nitride-metal (MNM) capacitors. The input matching network consists of a two-stage, lowpass impedance-matching transformer using the series inductance of bond wires and the capacitance of shunt MNM capacitors soldered to the metallized ground plane. The output matching network consists of shunt inductive bond wires connected from the isolated collector-die attachment area to DC blocking capacitors (also mounted on the metallized ground plane) and series inductive bond-wires connected between the collector area and the output package lead.
At fundamental frequencies, the optimum source and load impedances, ZSopt and ZLopt, respectively, for the silicon BJT used in the power amplifier design were determined using an in-house load-pull system. The device was characterized using a pulsed signal (150 s pulse width for a 10-percent duty cycle) in the frequency range from 1.2 to 1.4 GHz and where the collector is biased at +44 VDC. Optimum impedances were measured at the package reference planes and are listed in Table 1.
The use of internal impedance matching elements increases the impedance levels present at the terminations of the transistor package, and also simplifies the requirements for external matching circuitry. The transistor's input matching circuit is synthesized to optimally match the source impedances Zsopt at fundamental frequencies in the range from 1.2 to 1.4 GHz, presenting a short circuit at the second harmonic of the mid-band frequency (1.3 GHz). Class C bias is normally applied to a silicon-bipolar transistor by connecting a low-resistance RF choke between the device's base and emitter terminals, biasing the transistor into cutoff. External output matching consists of presenting near optimum impedances at the fundamental frequencies of interest. Second-harmonic signals are presented with low impedances by adjusting the length of the microstrip transmission line connected to ground via a bypass capacitor. The impedances of the third harmonics are optimized to enhance the collector efficiency over the frequency range of operation.
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The collector supply is connected to the collector terminal through an RF choke capable of handling high current densities. A series resistive-capacitive (RC) network connected from the collector bias line to ground is used to suppress instabilities by lowering the bias circuit impedance over the video bandwidth of the signal. The overall circuit was synthesized using Advanced Design System (ADS) simulation software from Agilent Technologies. The circuit was fabricated on 25-mil-thick RT/duroid printed-circuit-board (PCB) laminate from Rogers Corporation with dielectric constant of 10.5.
To demonstrate amplifier performance, a test fixture was built in which SMA connectors could be attached at input and output RF terminals. A high-voltage 100-F storage capacitor was soldered to the test fixture's biasing circuit. Finally, a heat-dissipating aluminum fin was mounted on the bottom of the PCB device carriers and an air-cooling fan was used to cool the amplifier during test (Fig. 3).
The amplifier was tested with 150-s-pulse-width signals at a 10-percent duty cycle and biased at +44 VDC (Figs. 4, 5, and 6). The peak output power was measured at the midpoint of the pulse (75 s into the pulse). As shown in Fig. 4, 490 W minimum output power was obtained at 1.4 GHz with 55 W input drive power, which corresponds to 9.5 dB power gain at that frequency. At 1.2 GHz, 550 W output power was measured for the same input drive power. The amplifier's power gain flatness is better than 0.6 dB. The minimum collector efficiency is 57 percent for 55 W input drive power. Table 2 presents the measured second and third harmonics relative to fundamental-frequency output-power levels. The typical amplitude droop is less than 0.15 dB, which indicates an excellent thermal design. The input return loss is better than 14 dB across the frequency range of 1.2 to 1.4 GHz. The amplifier has shown to be stable when operating into a VSWR load of 1.50:1 and rugged enough to handle a load VSWR of 2.0:1 at all phase angles.
The authors wish to thank Dr. William Leighton for useful technical discussions.
1. O. Pitzalis. Jr. and R. A. Gilson, "Broadband microwave Class-C transistor amplifiers," IEEE Transactions on Microwave Theory and Techniques, Vol. 21, No. 11, November 1973, pp. 660668.
2. Merrill I. Skolnik, Introduction to Radar Systems, McGraw-Hill, New York, 2001.
3. F. H. Raab, "Class-F Power Amplifiers with reduced conduction angles," IEEE Transactions on Broadcasting, Vol. 44, No. 4, December 1998, pp. 455459.
4. F. H. Raab, "Class-F Power Amplifiers with Maximally Flat Waveforms," IEEE Transactions on Microwave Theory and Techniques, Vol. 45, No. 11, November 1997, pp. 2007-2012.