The processing power provided by this latest generation of high-resolution analog-to-digital converters enable the design of software-defined radios with even fewer analog front-end components.
Software-defined-radio (SDR) architectures are not only commonplace in modern tactical radio designs they also form the basis for many newer test systems, especially those that must perform measurements across a range of communications standards. In spite of the versatility from digital signal processing, SDRs still rely on several stages of analog/microwave front-end processing. Yet, with the availability of the ADC12D1x00 family of high-speed analogto-digital converters (ADCs) from National Semiconductor, SDR equipment designers can now eliminate at least one down-conversion stage and its associated components.
The ADC12D1x00 family consists of three ADCs that can be used as two-channel devices or with the two channels interleaved for maximum sampling speed: the model ADC12D1800 (Fig. 1) with sampling speeds to 3.6 GSamples/s in single-channel interleaved mode, the model ADC12D1600, which runs to 3.2 GSamples/s in single-channel use, and the model ADC12D1000, with sampling rates to 2.0 GSamples/s for single-channel operation. All three provide 12-b resolution with low distortion and wide dynamic range with the capability of handling modulated signals within wide input bandwidths, making them well suited for SDRs and other military and commercial applications. The flagship converter in the line, model ADC12D1800, features a noise floor of -147 dBm/Hz (Fig. 2) with noise power ratio (NPR) of 52 dB and -61 dB fullscale (FS) intermodulation-distortion (IMD) level. The firm's three PowerWise ADCs should find applications not only in military communications, signal intelligence (SIGINT), and radar systems, but also in lightdetecting-and-ranging (LIDAR) systems as well as commercial multichannel video set-top boxes.
Because they can essentially directly digitize RF and microwave signals, these ADCs allow designers to eliminate at least one mixer, its filters, and local oscillator (LO) in an SDR analog front end, along with the associated problems of spurious generation and LO feed-through from those components. For example, in military radar and SDR radio systems, a single ADC12D1x00 combined with a digital down-converter can replace the multiple mixers, filters, amplifiers, and LO stages used in traditional heterodyne double-conversion or triple-conversion radio implementations. On the commercial side, multiple-channel set-top boxes, which typically incorporate one circuit card per channel tuner, can replace all of those tuners and circuit boards with a single ADC12D1x00 series ADC. In addition to the cost savings, the reductions in size, weight, and power consumption are dramatic, not to mention the flexibility afforded by using digital signal processing for the video tuning.
Each ADC actually contains a pair of 12-b ADCs with on-chip clock management to maintain precise timing. They include circuitry for multi-chip synchronization, programmable gain and offset adjustment per channel. The internal track-and-hold amplifier and extended self-calibration scheme enable a very fl at response of all dynamic parameters for input frequencies exceeding 2 GHz, while providing an exceptionally low 10-18 code error rate. The converters include an LVDS interface and provide LVDS outputs compatible with IEEE 1596.3-1996 standards. All three converters are designed for use with a single power supply. The high-speed model ADC12D1800 can be configured as a GSamples/s single-channel ADC or as a pair of 1.8-GSamples/s ADCs in the same package. Differential analog inputs are internally terminated and buffered, with interleaved timing handled automatically; a manual skew adjustment is also provided for applications requiring special timing conditions between channels. The ADC12D1800 offers a full-power bandwidth of typically 2.15 GHz with a typical noise floor of -147 dBm/Hz in interleaved single-channel mode. As a dual-channel 1.8 GSamples/s device, it provides a typical signal-to-noise ratio (SNR) of 57.8 dB with effective number of bits (ENOB) of typically 9.2 b and spurious-free dynamic range of typically 67 dBc. The full-power bandwidth in dual-channel mode is typically 2.8 GHz. In both modes of operation, the power consumption is typically 4.1 W.
The ADC12D1600 ADC offers a full-power bandwidth of typically 2.15 GHz sampling at 3.2 GSamples/s in interleaved single-channel mode with typical noise floor of -147.5 dBm/ Hz, typical NPR of 52 dB, and typical third-order intermodulation distortion of -63 dB FS. In dual-channel mode, sampling a 125-MHz input signal at 1.6 GSamples/s, it has a typical full-power bandwidth of 2.8 GHz with SNR of typically 58.6 dB, ENOB of typically 9.3 b, and SFDR of typically 68 dBc. It typically consumes 3.8 W power in both single-channel and dual-channel operation.
The lowest speed ADC, model ADC12D1000, has a full-power bandwidth of typically 2.15 GHz sampling at 2.0 GSamples/s in interleaved single-channel mode with typical noise floor of -147.5 dBm/ Hz, typical NPR of 52 dB, and typical third-order intermodulation distortion of -66 dB FS. In dual-channel mode, sampling a 125-MHz input signal at 1.0 GSamples/s, it has a typical full-power bandwidth of 2.8 GHz with SNR of typically 59.1 dB, ENOB of typically 9.5 b, and SFDR of typically 70.5 dBc. It typically consumes 3.4 W power in both single-channel and dual-channel operation.
The 12-b ADCs are supplied in a leaded or lead-free, 292-ball, thermally enhanced ball-grid-array (BGA) package, and are pin-compatible with the company's models ADC10D1000 and ADC10D1500 ADCs. The 12-bit ADCs are powered by a single +1.9-VDC supply. They are rated for operating temperatures from -40 to +85C.
National Semiconductor Corp., 2900 Semiconductor Dr., PO Box 58090, Santa Clara, CA 95052-8090; (408) 721-5000, Internet: www.national.com.