With biasing techniques such as those used for power amplifiers, an image-reject mixer fabricated with a standard CMOS process can deliver improved linearity.

Mixer linearity is critical to the performance of direct-conversion receivers with low intermediate frequencies (IFs). By biasing a low-IF image-reject mixer designed for a fully duplex system, such as UMTS, it is possible to achieve outstanding linearity even in the presence of large blocking (interference) signals, and even in a UMTS system, where the transmit signal is often the largest blocking signal for the receiver. The mixer is designed for bias in the Class AB region and is meant for use with a highly linear low-noise amplifier (LNA).

The image-reject mixer * (Fig. 1)* consists of eight switching transistors and four transconductors, with the IF at 100 MHz rather than at DC (0 Hz). It directly downconverts a received signal to a low IF using fewer parts and local oscillator (LO) stages. The image reject direct-conversion method has the added advantage of requiring fewer filtering components.

However, these advantages are somehow mitigated by the added problems of a receiver more prone to flicker (1/f) noise, the challenge of achieving good DC rejection, and linearity issues with high second-order and third-order intermodulation products.

The second-order products, characterized by the second-order intercept point (IP2), can be a particular problem in direct-conversion receivers^{1} since the second-order nonlinearity also demodulates the amplitudemodulation (AM) component of the amplitude-modulated blocker down to baseband, reducing the receiver's blocking margin. In addition, due to the possible presence of closely spaced interferers, the downconverter also requires a high IIP2.

Due to the reduced amount of filtering, a direct-conversion receiver is more sensitive to intermodulation products, requiring a down-converter mixer with high input third-order intercept point (IIP3). Although the IIP3 can be improved by adjusting bias levels and device size, IIP2 improvements are typically achieved by improving the symmetry of the design, improving the quality of the LO signal, and improving the LO-to-RF port isolation of the mixer. Low-IF receivers must deal with LO feedthrough, with RF and LO signals at similar frequencies. Although direct interference of LO with RF is not an issue in a low- IF receiver, LO phase noise and phase stability can impact how an incoming RF signal is processed. To avoid this, the LO is usually operated at twice the required frequency and then divided by two.

Since enhancement-mode CMOS transistors are essentially surface devices, they exhibit far more 1/f noise offset through about 100 MHz than devices fabricated with other semiconductor processes, due to the phenomenon of charge trapping. This can impact system noise figure since it adds FM noise that in return restricts the data that can be received by the discriminator circuit.

The image-reject mixer is a quadrature Gilbert-type direct-conversion mixer * (Fig. 2)*. It consists of eight switching transistors (M5 to M12) and four transconductors (M1 to M4), arranged in symmetry. A pair of switching transistors and a single transconductor constitutes a single-balanced mixer. Each of the differential inputs to the mixer has a transconductor stage based on a single NMOS device. The transconductor converts available voltage to current to be mixed by the upper section of the switches, operated at the LO frequency. The upper switching section is controlled both by a gate bias and by the LO signal at its input. The applied gate bias thus acts as an offset voltage to the mixing action of the circuit. Sharp transitions in the LO signal reduce the zero-crossing noise contribution and nonlinearity.

Flicker nose is contributed by two mechanisms^{2}: the zero crossing of the tail current (the direct method) and the induced current in the tail capacitance (the indirect method). Larger capacitive gates tend to reduce the flicker noise as they filter out some of the noise.^{3} The width of the transistor has been set to 1.5 mm, which is rounded from the recommended width of 1.54 mm for optimum F_{T}.

The minimum noise figure is illustrated in Eq. 1 ^{4}.

where

? = the body coefficient,

d = the gate noise coefficient, and

c = the correlation coefficient.

Due to the frequency-conversion requirements when working at low IFs, the use of reactive components is not feasible and active loads result in excessive noise. Because of this resistive loads are used, although they add to voltage consumption. The specifications for the image-reject mixer were derived from the overall specifications for the UMTS receiver as well as the LNA's design specifications. Given that the 3GPP5 UMTS standard specifies a maximum of -43 dBm at the receiver input for high gain selection, this then provides the values shown in * Table 1*. It includes a listing for the maximum signal present under typical conditions at the input of a receive demodulator mixer. But because the system is full duplex, and the transmit signal can also be present at the receiver's input, the mixer must be able to handle a relatively high input level under full-duplex conditions

*.*

**(Table 2)** The conversion gain, Gc, of the image-reject mixer can be calculated from Eq. 3 _{8}:

Since voltage gain, A_{V}, is equal to the output voltage divided by input voltage,

If the degeneration resistance, R_{Source}, is approximately equal to zero, then

The optimum transistor width, w_{opt}, is derived from Eq. 6^{8}:

from which it can be deduced that the larger the value of input impedance, R_{in}, the smaller the value of w_{opt} and the lower the C_{gs} and C_{gd} capacitances. The lower the junction capacitance, the higher the value of F_{T}. implying a better noise figure.

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The w_{opt} value for the transconductor devices can be found by assuming the mixer impedance is 50 Ohms. Using a frequency of 2.1 GHz for UMTS and from ref. 9 values of Cox = 0.86 fF/Î¼ m and _{eff} = 0.38 m, the value of w_{opt} is 1.54 mm, rounded off to 1.5 mm (from Eq. 6) and, from ref. 8,

and from ref. 10, the transconductance, g_{m}, is defined as

Given that the device is intended to operate in saturation, the junction capacitances are defined as follows^{11}:

and

From the CMOS process manual^{9} C_{ov} = 0.12 fF/m and n = 370 cm_{2}/ V_{s}, where Cov is the overlap capacitance per unit area, n is the electron mobility, C_{gs} is the gate-source junction capacitance, and Cgd is the gatedrain junction capacitance. From this, C_{gd} = 180 fF and C_{gs} = 481 fF, and since the CMOS device cutoff frequency (F_{T}) is 25 GHz^{9}:

which yields a g_{m} of 104 mS. Assuming that the mixer has a load impedance of 450 Ohms, the voltage gain from Eq. 5 is a significantly high linear voltage gain of 29.8.

Having previously calculated the required input power at 1-dB compression (P1dB) for the mixer to be +3.4 dBm or more, and performing the gain equations above, it is necessary to reduce current across the device to improve linearity. The mixer's devices must be biased in the unsaturated region or even in the weak inversion layer. In power amplifier terminology, this could be categorized as Class B or Class AB operation.

For A_{V} = 2.2 (linear gain), R_{L} = 450 Ohms, then from Eq. 4:

The gain of the transconductor transistors (M1 to M4 I * Fig. 2*) can be calculated as in

*.*

**Table 3** The mixer's input P1dB point can be calculated from Eq. 12^{12}:

where

Larger LO power requirements indicate a larger drain current require ment through the switching quads. However, the larger the value of drain current, the greater will be the amount of flicker noise. There is merit in lowering the drain current and increasing the load resistors to improve the gain.

In an active mixer, DC biasing is usually implemented to compensate for LO power levels. In other words, the common-mode voltage can be increased to compensate for higher switching LO power requirements.

Two important points to bear in mind in biasing the mixer is to ensure that (1) when there is no voltage at the gate of the transconductor stage of the mixer, the current through the mixer should be zero, and (2) the commonmode voltage of the switching mixer is the zero crossing point. At this point, the mixer current should be zero. Better switching is always performed by an ideal square wave signal. For this work, the signal to the image-reject mixer is fed externally, typically via a frequency divider. This produces what is called a square-sine-wave signal, since the divider acts as an over-saturated amplifier to give square edges to the sine wave. The external LO signal supplied for this work is specified as PLO = -5 dBm 2 dB.

Flicker noise is difficult to filter and is expressed by Eq. 14. ^{2}

From * Fig. 3* it can be seen that LO power level affects mixer noise figure performance; for power levels above 3 dBm, the improvement is small. The explanation is that beyond a certain power level, the switching gates are sufficiently open and the resistive contribution of the mixer is reduced. In other words, the mixer is switching between an "on" state and an "off" state. Beyond this point, the extra reduction in noise figure may be due to the improved on resistance, R

_{on}, of the mixer and the extra generator affects of the channel length modulation.

The mixer is divided in to two sections, the transconductor stage, from M1 to M4 in * Fig. 2*, and the switching stage, from M5 to M12 in

*. For ease of implementation, the imagereject mixer was designed in submodules, one for the two transconductors and the other with two switches. The image-reject mixer consists of two transconductor blocks and four switching blocks.*

**Fig. 2**Continue to page 3

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The circuit in * Fig. 4* is symmetrical to ensure good LO and harmonic suppression, and high IP2. The inputs are matched to the conjugate impedance of the proceeding LNA, for maximum signal transfer at the desired frequency band. The NMOS transistors in

*are maintained at a maximum width of 1.5 mm for optimum F*

**Fig. 5**_{T}performance. This minimizes flicker noise while maintaining conditions for optimum thermal noise, as shown in Eq. 1. The input port voltage reflection coefficient is very good (

*). The S*

**Fig. 6**_{11}input return loss indicates that the input port is well matched as it is near the center of the Smith chart.

* Figure 7* shows a differential mixer gain of 5.96 dB. The gain obtained in initial bias calculations for linear gain per balanced mixer was 6.8 dB (

*). The 1-dB discrepancy could be attributed to parasitic losses and transistor second-order effects.*

**Table 2** The mixer's noise figure varies from 22 dB at offset of 10 MHz to 14.7 dB at an offset of 100 MHz from the 0-Hz DC point (* Fig. 8*). The high values near DC are as a direct result of the flicker noise contribution that exists in all surface devices.

*shows the overall receiver noise figure for a UMTS handheld terminal designed with this mixer, the front-end duplex filter of ref. 6, and LNA of ref. 7. Allowing 2-dB margin of error, the maximum noise contribution must not exceed 9.4 dB in the receiver.*

**Table 4**^{13}

The input compression point of the mixer/de-modulator circuit is just under +3.7 dBm at the input. This is deemed sufficient to provide a linear translation of the amplified RF signal to a low IF for detection.

REFERENCES

1. Behzad Rezavi, "Design Considerations for Direct- Conversion Receivers," *IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing*, Vol. 44, No.6, June 1997.

2. H. Darabi and A. A. Abidi, "Noise in RF-CMOS mixers: A simple physical model," *IEEE Journal of Solid-State Circuits*, Vol. 35, October 2000, pp. 1528-1545.

3. H. Sjoland, A.Karim-Sanjaani, "A Merged CMOS LNA and Mixer for a WCDMA Receiver," *IEEE Journal of Solid-State Circuits*, Vol. 38, June 2003, pp. 1045-1050.

4. Thomas H Lee, *The Design of CMOS Radio-Frequency Integrated Circuits*, 2nd Ed., Cambridge University Press, p. 369, 2004.

5. The 3 GPP UMTS Standard: www.3gpp.org.

6. EPCOS Components. Available online at: www.usa.epcos.com/Web/share/all/files/RFProducts/WCDMA.pdf.

7. N. Logan and J. M. Noras, "Merits of a SiGe Bipolar LNA over a silicon CMOS LNA at 2.1 GHz," 9th International IEEE Conference on Telecommunications in Modern Satellite, Cable and Broadcasting Services, 2009.

8. Thomas H. Lee, *The Design of CMOS Radio-Frequency Integrated Circuits*, 1st ed., Cambridge University Press, 1998, pp. 156, 177, 382, and 419.

9. Austriamicrosystems Process Manual, ENG-182 rev 4, pp. 12-24, www.Austriamicrosystems.com.

10. B. Rezavi, RF Microelectronics, Prentice-Hall, Upper Saddle River, NJ, 1998, p. 21. 11. Randall L. Geiger, Phillip. E. Allen, and Noel. R Strader, *VLSI Design Techniques for Analog and Digital Circuits*, McGraw-Hill, New York, 1990, p. 165.

12. RF IC Design web site: www.rfic.co.uk.

13. O. K. Jensen, T. E. Kolding, Chris. R. Iversen, S. Laursen, R. V. Reynisson, J. H. Mikkelsen, E. Pedersen, M. B. Jenner, and T. Larsen, "RF Receiver Requirements for 3G WCDMA Mobile Equipment," *Microwave Journal*, Vol. 43, No. 2, February 2000, pp. 22-46.