Addressing demanding frequency-synthesizer requirements often call for some design flexibility. The basic phase-lock-loop (PLL) frequency synthesizer provides reasonable spectral purity and frequency agility at low cost, in a spaceefficient, low-power package, and has been at the heart of radio-frequency (RF) systems for some time. However, in cases requiring fast switching speed or low levels of phase noise or spurious signals, the use of a more complex architecture may be necessary. With an appropriate design approach, the use of a modern, low-cost, highly integrated PLL and direct-digital synthesizer (DDS) integrated circuit (IC) in combination can greatly facilitate the implementation of high-performance architectures.

The majority of high-frequency systems are well served by either traditional integer-divider-based designs (as shown in Fig. 1), or fractional-N-divider-based designs. In either case, the required functionality can typically be achieved by the use of a single general-purpose frequency-synthesizer IC, together with an external voltage-controlled oscillator (VCO). The VCO function may be performed by an IC, a module, or a discrete component solution, or may even be internal to the synthesizer chip, depending on the required frequency range, phase-noise performance, and space, cost, and power constraints. The final design can usually be based around the manufacturer's application notes, and often a downloadable application is available to load the synthesizer registers and set up the phase detector gain, etc.

However, for certain very demanding applications, the performance of basic architectures may be found to fall very far short of that required, particularly in terms of phase noise, levels of spurious signals and frequency switching speed. Examples of such applications are frequency synthesizers for use in Doppler radar systems, and communication systems that make use of fast frequency switching and/or high-order modulation schemes at microwave frequencies.

To illustrate, if an application requires a relatively small tuning step size at a high output frequency, in an integer PLL synthesizer this would dictate a high division ratio, which would result in a high phase noise floor within the loop bandwidth . For a 5-GHz output frequency and a channel spacing of 100 kHz, the required division ratio of 50000 would result in a noise floor limit within the loop bandwidth of 94 dB above that of the phase detector, or typically around -75 dBc in a 1-Hz bandwidth. Typical fractional-N frequency synthesizer ICs may achieve a figure of around -85 dBc in a 1-Hz bandwidth.

Although direct analog frequency synthesizers (effectively comprising switch-selectable frequency multipliers, mixers, and filters) may excel in terms of switching speed and phase noise, their implementation will typically be much more complex, particularly if good spurious signal performance is required. Digital-direct synthesizers (DDS) provide fine tuning steps, fast frequency switching speed, and good phase noise, but are unable to provide outputs at microwave frequencies directly, without the use of additional frequency multiplication.

Although not specifically targeted for use in such designs, the types of PLL and DDS devices developed for more common applications may however often be usefully applied as building blocks in more complex, higherperformance architectures. Figure 2 shows an example of a PLL-based architecture that may be employed to achieve an improved phase noise performance. Here, the output of the VCO is first downconverted to a much lower frequency before being applied to the input of the frequency synthesizer IC. The required division ratio is therefore lower, reducing the noise contribution from the phase detector. For the example shown, the division ratio would be reduced from 50000 to 2000, and the limit on the phasenoise floor within the loop bandwidth would improve by 28 dB to -103 dBc. For a wideband application, several stages of downconversion may be employed, with local-oscillator (LO) frequencies being switch-selected to keep the required N value low.

A change of architecture can also be useful in achieving a fast frequency switching time. The time taken for a PLL to settle to a new frequency will be inversely proportional to the bandwidth of the loop. In simple architectures, a requirement for a small channel frequency spacing will dictate the use of a narrow loop bandwidth, resulting in a loop that is slow to settle a frequency step. In an integer-PLLbased design, the reference frequency will be equal to the step size, and the loop bandwidth must be around an order of magnitude smaller than this. In a fractional-N-based design, although the reference frequency may be kept much higher, the loop filter must typically still provide a high attenuation of the products that fall at multiples of the step size, placing an upper limit on the loop bandwidth. However, by employing a DDS as a high-frequency reference source within a PLL, the division ratio can be kept to a low value (thus minimizing noise), while a very small step size may be achieved without the need to constrain the loop bandwidth.

Modern DDS ICs can generate an output in the very-high-frequency (VHF) region with millihertz tuning step sizes, and excellent phase noise in a small footprint package. Frequency and phase modulation capabilities are often also included. Close-to-carrier spurious signal levels are determined by the resolution of the phase-lookup table and output digital-to-analogconverter (DAC) and are typically very good (around -80 dBc); however, other sampling products will be present at the output at much higher levels. By using a DDS IC as a source for a frequency reference within a PLL, the output frequency may be translated to whatever frequency is needed, while the unwanted sampling products may be effectively filtered out by the PLL. Figure 3 offers an example of such an architecture.

The PLL may be thought of as providing a tracking filtering function, which is very beneficial as it allows the large unwanted sampling products at the DDS output to be greatly attenuated, along with other products generated by the downconversion process. Depending on the levels of spurious signals that may be tolerated, the PLL may be required to provide little or no extra attenuation of the already low in level close-to-carrier spurious signals. The loop bandwidth of the PLL may therefore be kept much larger than would be practical in a conventional PLL synthesizer, resulting in improved frequency switching speed. The PLL reference frequency may be made much higher than the DDS frequency step size, and the division ratio very small, resulting in good phase noise performance. As a greater loop bandwidth equates to a greater loop gain at a particular offset, and given the lower noise contribution from the phase detector, the component of the noise contributed by the VCO will also be reduced.

It should be noted that careful attention must be paid to the detail of the frequency plan in such an architecture. The frequencies of the reference oscillator, DDS clock source and PLL reference must be carefully chosen with reference to the required channel spacing, in order to both minimize the complexity of the required reference generation hardware and avoid the generation of close-to-carrier spurious signals that cannot be filtered.

As mentioned above, many DDS ICs feature frequency and phase modulation capabilities, and these may be used where a modulated output is required, for example to generate the linear frequency ramps required for a frequency-modulated-continuouswave (FMCW) radar. In practice, in order to minimize spurious outputs, it may be most appropriate to add the modulation using a more elaborate architecture, such as by an additional tracking loop, as shown in Fig. 4.

Particularly in the case of wideband systems, frequency switching speed may be greatly improved by the use of a feedforward technique. An example is shown in Fig. 5. When a command to change frequency is received, the loop is broken, and the VCO control voltage is then steered by a DAC to a value predicted to correspond to that of the required new output frequency. The loop is then closed again, and the PLL acts to settle out any residual phase and frequency errors. In practice, the control voltage may be steered very quickly to a value close to that required, and as the PLL has only to settle the small residual error, the total settling time of the system will be greatly reduced. Note that in addition to speeding up the settling process, this arrangement actually proves to be essential in wideband systems that use a number of frequency conversion stages within the loop, as without it, the PLL may not have a sufficient capture bandwidth to settle a large step. In order to achieve tightly controlled time sequencing of the channel change process, the control logic function is best performed by an FPGA. In practice, for devices having a serial control interface, the time taken to write the required register data may be the most significant factor in determining the switching time that can be achieved.

A practical microwave frequency synthesizer based on the above techniques may simultaneously achieve low spurious content, fast switching speed, and excellent phase noise, while offering frequency modulation (FM) and phase modulation capabilities. Given a careful choice of architecture and frequency plan, the use of modern PLL synthesizer and DDS ICs under the control of field-programmable- gate-array (FPGA)-based logic enables this high level of performance to be achieved in a power-and-spaceefficient package (Fig. 6).