MOST 40-Gb/s AMPLIFIERS suffer from limited gain, as the gain is often sacrificed for adequate bandwidth in high-speed operations. To conquer these design limitations, a circuit structure for broadband amplifiers has been proposed by Jun-Chau Chien and Liang-Hung Lu from the Department of Electrical Engineering and Graduate Institute of Electronics Engineering, National Taiwan University, Taipei. In this new architecture, the gain cells in the conventional distributed amplifiers are replaced with cascaded stages. The result is enhanced gain. Thanks to the use of inductive peaking with the staggertuning technique, a 3-dB bandwidth also can be achieved while maintaining impressive gain flatness across the entire frequency band.
In standard 0.18-m CMOS technology, two amplifiers are implemented for this proposed circuit architecture. The amplifier with a 3 x 3 configuration flaunts 16.2 dB of gain and a 3-dB bandwidth of 33.4 GHz. In contrast, the 2 x 4 amplifier demonstrates a gain of 20 dB and a bandwidth of 39.4 GHz. Both circuits consume 260 mW of direct-current (DC) power from a 2.8-V supply voltage. In doing so, they succeed in providing an eye diagram with a clear eye-opening with a pseudo-random bit sequence (PRBS) at 40 Gb/s.
For the cascade stage, a broadband technique is introduced that incorporates shunt as well as series peaking. For cascade stages with inductive peaking, the proposed design methodology incorporates the stagger-tuning technique. This approach should simplify the circuit implementation while minimizing undesirable gain ripples. See "40-Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18-m CMOS," IEEE Journal of Solid-State Circuits, Dec. 2007, p. 2715.