This body-biased voltage-controlled oscillator provides reasonably good phase-noise performance over a broad tuning range with relatively low power consumption and low jitter timing noise in the time domain.

**M. Moghavvemi, H. Ameri, and A. Attaran**

Voltage-controlled oscillators (VCOs) are an integral part of frequency synthesizers using phase-locked loops (PLLs) and clock and data recovery (CDR) circuits.^{1} Phase noise is one of the most critical characteristics of the wireless communication systems and it is based on static behavior in the device oscillation.^{2} In wireless communication systems, wide bandwidths with reliable phase noise performance is extremely critical; hence the phase noise performance has been improved by number of novel VCO structures.^{1-6}

In this article, a novel dynamic-threshold (D_{T}) metal-oxide-semiconductor (MOS) (DTMOS) technique has been applied to increase the operating bandwidth of a VCO by reducing the threshold voltage (V_{T}) of a PMOS load transistor to achieve faster transitions and higher operating frequencies. The three-stage VCO has a center frequency of 14 GHz with tuning range of 12 to 16 GHz and phase noise of -101 dBc/Hz offset 100 kHz from the carrier.

In this novel VCO design, the reduction of threshold voltage V_{T} results in an exponential increase in the static power. This is a drawback in silicon-based technologies,^{3} but having dynamic control over V_{T} can be a benefit in some oscillator designs. It helps overcome supply variations and noise injection,^{4} and eliminate parasitic capacitors in the transistor (gate-source, gate-base, and gate-drain capacitances CGS, CGB, and CGD, respectively)and device body effects when the PMOS transistor is turned off. This control can lead to broadband VCO tuning. The DTMOS approach works best with a low voltage supply; as a result, it is ideal for high-frequency applications requiring a low-voltage supply.

In a traditional VCO design (**Fig. 1**), a PMOS device is employed as resistor. Gate-source voltage V_{GS} is used to steer the frequency oscillation of the VCO. However, by changing V_{GS}, threshold voltage V_{T} varies dramatically, resulting in significant change in V_{GS} V_{TH}, resulting in the PMOS device not functioning as a resistor and the VCO circuit failing to oscillate.

To maintain a PMOS device in the Ohmic region, the relation V_{DS}GS V_{T} must be valid. As long as VGS steers the frequency, V_{G} cannot be changed over a wide-enough range for truly wideband tuning. Altering V_{G} causes the PMOS device to operate in the saturation region, leading to a failure to oscillate.^{6}

Figure 2 shows the body-biased delay-cell topology for the proposed broadband VCO. This method guarantees that V_{GS} is always equal to V_{DD} hence the PMOS operating region will never go into saturation. By employing this bulk connection to the voltage control, there is a need to consider the influence of the source-to-body voltage, on threshold voltage V_{T}:

V_{TH} = V_{TH0} + Γ(V_{SB} + |2f_{f}|)0.5 (|2f_{f}|)^{0.5} (1)

where

V_{TH0} = zero-bias threshold voltage, f_{f} = the Fermi potential, V_{SB} = the source-to-body voltage, and Γ = the body effect coefficient.

The values of the minimum threshold voltage, V_{tmin}, and the maximum threshold voltage, V_{tmax}, based on variations in V_{SB} are shown in Fig. 3. Higher amplitudes of cause wider depletion regions for longer durations. This results in a wider voltage control range. Equation 1 impacts two cases: when V_{B} is at a minimum and when V_{B} is at a maximum.

In the first case, when V_{B} = 0, the relationship of V_{SB} with threshold voltage V_{T} is significantly small, but not negligible. This relationship provides a wide tuning range of V_{B} for steering the control voltage. When the bias voltage is zero, V_{SB} is equal to VDD. Hence,

V_{TH} = V_{TH0} + 0.7 V. Threshold voltage V_{T} is at a maximum value, resulting in a slow transition. This represents the worst-case scenario for the PMOS device to operate in the linear region, and leads to a lower-frequency tuning range for the VCO.

In the second case, when V_{B} = 4 V, and the control voltage is at its maximum, VSB is equal to zero, and, in Eq. 1, V_{TH} = V_{TH0}. This gives the minimum for V_{T}, which leads to a faster PMOS transition, and upper-frequency range for the VCO circuit.

Figure 3 shows behaviors for V_{tmin} and V_{tmax}. The second case is similar to the operation of a traditional VCO, in which the zero control voltage is biased to the gate connection to achieve higher-frequency operation. In this second case, when V_{B} = 4 V, the high voltage biasing configuration cannot be applicable unless using a thickgate PMOS transistor. Normally, thin-gate PMOS transistors cannot take more than 1.5 V because the electrical overstress (EOS) voltage will damage the device and ultimately lead to device breakdown.

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For semiconductors, EOS presents a range of electrical threats due to electromagnetic pulse (EMP) and electrostatic discharge (ESD) effects. Device failure is the result of overloading the gate connection with too high a voltage. But in the proposed VCO design, the gate connection is grounded, allowing an increase in the bulk voltage, V_{B}; the rate at which positive charges in the depletion region discharge through the gate connection to ground increases as a result of this configuration. The higher amplitude of V_{B} causes a wider depletion region to last for a longer time over a wider control voltage range.

Figure 4 shows an MOS small-signal equivalent circuit for modeling high-frequency operation. Setting VG to zero eliminates the parasitic effects of C_{GS}, C_{GD}, and C_{GB} and also increases V_{GS}, which leads to an incremental increase in current source g_{m}V_{GS}. Biasing the device body to a voltage greater than zero results in decreases of C_{BD}, C_{BS}, and a decrease in V_{SB}, which decreases the leakage current of g_{mb}V_{BS}. Each VCO delay cell has a capacitance value of C_{total} which can be calculated by Eq. 2. By substituting C_{total} into Eq. 3, the VCO frequency can be calculated:

C_{total} = C_{GS} (in CMOS) + _{CGB} (in PMOS) + C_{DB} (in PMOS) (2)

F_{center} = 1/(2nRC_{total}) (3)

In Eq. 2, the decrease of CGB (in PMOS) and C_{DB} (in PMOS) results in an increment of the upper frequency limit, leading to a more wideband VCO.

By biasing the bulk connection to a voltage greater than zero (Fig. 5), more electrons are attracted to the device substrate connection, leaving a larger positive charge. Therefore, the depletion region becomes wider. In Eq. 4, V_{T} is proportional to total charge in the depletion region because the gate charge must mirror Q_{d} before the inversion layer is formed^{6,7}:

V_{TH} = f_{ms} + 2f_{f} + (Q_{dep}/C_{ox}) (4)where f_{ms} is the difference between the work function of the polysilicon gate and the silicon gate, and

f_{f} = (KT/q) ln(N_{sub}/N_{i}) (5)

Q_{dep} = (4qe Sif_{f}V _{sub}) ^{0.5} (6)

Note that the gate voltage is always zero. This configuration results in 1) discharging the large positive charge load in the depletion region due to positive body biasing, 2) fast forming in the channel between the drain and source connections, and 3) fast discharging of the charge load though the gate connection into ground, which finally leads to a much faster transition in an MOS device. Figure 6 shows the three-stage ring VCO, while Fig. 7 provides the simulated output spectrum for the VCO. The Table compares wideband VCOs.^{8-12} The DTMOS methods shown here can be applied to achieve wideband VCOs capable of handling more than one communication channel, such as the example from 12 to 16 GHz with low phase noise of 101 dBc/Hz offset 100 kHz from the carrier. When fabricated on a multiproject wafer using a 0.13-m semiconductor process from Silterra, the power consumption is a low 8.64 mW because of the low voltage supply.

References

1. J. Savoj and B. Razavi, "A 10-GB/s CMOS clock and data recovery circuit with a half-rate linear phase detector," IEEE Journal of Solid-State Circuits, Vol. 36, 2001, pp. 761767.

2. F. Herzel and B. Razavi, "A study of oscillator jitter due to supply and substrate noise," IEEE Transactions Circuits and Systems II: Analog and Digital Signal Processing, Vol. 46, January 1999, pp. 56-62.

3. Wang Zheng, S. Huseyin, S. Savci et al., "1-V Ultra-Low-Power CMOS LC VCO with Dynamic Body Biasing," IEEE Journal of Signals, Circuits, and Systems, International Symposium, Vol. 1, July 13-14, 2007, pp. 1-4.

4. Assaderaghi Fariborz, "DTMOS: its derivatives and variations, and their potential applications," Microelectronics, ICM, 12th international conference, 2000, pp. 9-10.

5. Marc Rafal et al., "Microwave communications system," United States Patent No. 4475242, 1984.

6. Razavi Behzad, Design of Analog CMOS Integrated Circuits, McGraw-Hill, New York, 2000.

7. C. Lam and B. Razavi, "A 2.6 GHz/5.2 GHz CMOS voltage-controlled oscillator," IEEE Journal Solid- State Circuits, pp. 402-403, 1999.

8. Frank Herzel and Wolfgang Winkler, "A 2.5-GHz eight-phase VCO in SiGe BiCMOS technology," IEEE Transactions on Circuits and SystemsII, Vol. 52, No. 3, March 2005, pp. 140-144.

9. Lee Chihun and Cho Lan-Chou, "A 50.853-GHz Clock Generator Using a Harmonic-Locked PD in 0.13-m CMOS," IEEE Transactions on Circuits and SystemsII, Vol .55, May 2008, pp. 404-408.

10. Liu Ting-Ping, "A 6.5 GHz monolithic CMOS voltage-controlled oscillator," IEEE Transactions on Solid-State Circuits Conference, Digest of technical papers, 1999, pp. 404-405.

11. Lee Jri and B. Razavi, "A 40-Gb/s clock and data recovery circuit in 0.18-m CMOS technology," IEEE Conference on Solid-State Circuits, Vol. 38, pp. 2118-190, 2003.

12. Jae Hong Chang and C. Hoong-Ki Kim, "A symmetrical 6-GHz fully integrated cascode coupling CMOS LC quadrature VCO," IEEE Journal on Microwave and Wireless Components Letters, Vol. 15, October 2005, pp. 670-672