Get Full Synchronization Performance At Current Clock Speeds

July 15, 2008
SYNCHRONOUS CLOCKING SCHEMES provide clock signals that are frequency locked at every transmission/ reception exchange. Such systems permit seamless data exchange at the highest possible rates. Due to different design tradeoffs, however, ...

SYNCHRONOUS CLOCKING SCHEMES provide clock signals that are frequency locked at every transmission/ reception exchange. Such systems permit seamless data exchange at the highest possible rates. Due to different design tradeoffs, however, engineers often have to rely on asynchronous or plesiochronous systems instead of synchronous systems. NEL Frequency Controls (www.nelfc.com) has introduced a fourth option in its Synchronized Clock Oscillator technology. This technology does not require a master clock, fanout, phase-locked-loop (PLL) frequency locking, or multiplication. The company details this system in a 14-page white paper titled, "The Future of Multi-Clock Systems."

The white paper provides an overview of the roles played by clock signals in digital systems and techniques for distributing clock signals. In legacy synchronous systems, a common clock signal is distributed by fanning out a master clock to each system component. Several output buffers are used to re-drive a single input clock signal. Although those buffers have propagation delay, fanouts are available with PLLs to eliminate skew between the outputs. Unfortunately, PLLs introduce more jitter. If more than one fanout is required, adjustable delay should be included in the circuit to eliminate skew between fanout models. Some common techniques for clock distribution are discussed in this section.

A synchronous system's components must act in concert. In contrast, the component of an asynchronous system can be autonomous. The clock signal determines logic transitions at the transmitter. At the receiver, a separate clock must be at least temporarily phase and frequency locked so that bits can be sampled at their centers. Asynchronous architectures solve the problems of fanout and associated increased jitter. Having multiple clocks also reduces the possibility of catastrophic central clock failure.

Of course, moving from a synchronous to an asynchronous system involves sacrificing ultrahigh performance, which can only be attained in a system where every event occurs in harmony. The white paper provides an overview of several ways that asynchronous systems can achieve the level of synchronization necessary for communication. It also offers a brief explanation of plesiochronous systems, which have components with separate clocks. Although the frequencies of those clocks are nominally the same, they are not frequency locked. Although the point of this white paper is obviously to detail the advantages of this technology, it also succeeds in providing a solid overview of clocking schemes.

NEL Frequency Controls, Inc., 357 Beloit St., P.O. Box 457, Burlington, WI 53105-0457; (262) 763-3591, Internet: www.nelfc.com.

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