This trio of power-efficient analog-to-digital converters supports sampling rates to 1 GSamples/Sas well as programmable control of channel switching and operating modesfor applications through 1 GHz.
HIGH-SPEED ANALOG-TO-DIGITAL CONVERTERS (ADCs) for portable and low-cost test equipmentincluding oscilloscopesmust be fast and efficient, capable of capturing analog signals with high resolution and low power consumption. The HMCAD1520, HMCAD1511, and HMCAD1510 ADC family from Hittite Microwave Corp. is all this and more, delivering sample rates to 1 GSamples/s with 8-b resolution, and with the flexibility that programmability brings.
With increasing need for portable instrumentation for on-site and in-the-field measurements, instruments like portable oscilloscopes are growing more popular, boosting the need for high-performance, low-power ADCs such as Hittite's converters. All three devices feature programmable selection between single-, dual-, and four-channel operation, integrated cross point switch (analog multiplexer) array, and internal clock divider. All three provide LVDS digital outputs optimized for use in low-power designs, along with low-cost field-programmable gate arrays (FPGAs). And all three data converters can be configured on the serial peripheral interface (SPI) bus.
Models HMCAD1510 and HMCAD1511 are 8-b ADCs designed for single-channel sampling rates, from 120 to 500 MSamples/s and 120 MSamples/s to 1 GSamples/s, respectively. The devices operate with internal 13-b resolution, allowing for a 1x to 50x digital gain range with no missing codes for digital gain settings through 32x. The gain matching between channels is typically 0.5 dB.
The digital gain feature can be used in the place of analog gain as needed, since the signal-to-noise ratio (SNR) versus gain performance of these ADCs is superior to conventional 8-b ADCs (Fig. 1). The ADCs also feature differential nonlinearity (DNL) of typically 0.2 dB and integral nonlinearity (INL) of typically 0.5 dB.
Both the HMCAD1510 and HMCAD1511 are designed for +1.8-VDC supplies, with the former dissipating only 295 mW power when operating at 500 MSamples/s and the latter only 710 mW at 1 GSamples/s. Both feature fast start-up times: 0.5 s from sleep mode and 15 s from power-down mode. Both ADCs are supplied in 7 x 7 mm 48-pin QFN packages and both incorporate internal reference circuitry, with no external components required. The ADCs offer single-, dual-, and quad-channel operation, with the sampling rate scaling down as more channels are used. By way of example, the HMCAD1510 operates at sampling rates to 250 MSamples/s per channel with two channels and 125 MSamples/s per channel with four channels.
The HMCAD1510 ADC achieves 49.8-dB SNR with 1x gain and 48-dB SNR with 10x gain. It is characterized for signal-to-noise-and-distortion (SINAD) ratio performance and spurious-free-dynamic-range (SFDR) performance, both with and without interleaving spurious content. The typical SINAD performance including interleaving spurs is 47 dB in single-channel mode at 500 MSamples/s, 49.5 dB in dual-channel mode at 250 MSamples/s, and 49.6 dB in quad-channel mode at 125 MSamples/s. The typical SINAD performance excluding interleaving spurs is 49.4 dB in single-channel mode at 500 MSamples/s and with 10x digital gain, 47.7 dB in dual-channel mode at 250 MSamples/s, and 49.5 dB in quad-channel mode at 125 MSamples/s. The typical SFDR performance including interleaving spurs is 49 dB in single-channel mode at 500 MSamples/s, 59 dB in dual-channel mode at 250 MSamples/s, and 60 dB in quad-channel mode at 125 MSamples/s. The typical SFDR performance excluding interleaving spurs is considerably better, at 65 dB in single-channel mode at 500 MSamples/s and with 10x digital gain, 65 dB in dual-channel mode at 250 MSamples/s, as well as 69 dB in quad-channel mode at 125 MSamples/s.
The HMCAD1511 operates with maximum sampling rates of 1 GSamples/s, 500 GSamples/s per channel, and 250 GSamples/s per channel in single-, dual-, and quad-channel modes, respectively. It features SNR of typically 49.8 dB at 1 GSamples/s and 1x digital gain and 48 dB at 1 GSamples/s. The typical SINAD performance including interleaving spurs is 45.7 dB in single-channel mode at 1000 MSamples/s, 44.0 dB in dual-channel mode at 500 MSamples/s, and 49.2 dB in quadchannel mode at 250 MSamples/s. The typical SINAD performance excluding interleaving spurs is 49.3 dB in single-channel mode at 1000 MSamples/s, 49.0 dB in dual-channel mode at 500 MSamples/s, and 49.3 dB in quad-channel mode at 250 MSamples/s. The typical SFDR performance including interleaving spurs is 49 dB in single-channel mode at 1000 MSamples/s, 44 dB in dual-channel mode at 500 MSamples/s, and 57 dB in quad-channel mode at 250 MSamples/s. The typical SFDR performance excluding interleaving spurs is 64 dB in single-channel mode at 1000 MSamples/s and with 10x digital gain, 63 dB in dual-channel mode at 500 MSamples/s, and 70 dB in quad-channel mode at 250 MSamples/s.
The highest-resolution device of the trio is the model HMCAD1520, which can operate with either 12- or 8-b resolution in high-speed mode or with 14-b resolution in precision mode. In high-speed mode, the maximum sampling rate is 640 MSamples/s for 12-b resolution and 1000 MSamples/s for 8-b resolution. In precision mode, the converter provides 14-b resolution for a maximum sampling rate of 105 MSamples/s across four channels. In fact, by programming over the SPI bus, the HMCAD1520 can be configured to operate as an 8-b HMCAD1510 or HMCAD1511. As with the other ADCs, the HMCAD1520 can operate in single-, dual-, and quad-channel modes. In high-speed mode, the maximum respective sampling rates are 640, 320, and 160 MSamples/s for 12-b resolution with one, two, and four channels, and 1000, 500, and 250 MSamples/s for 8-b resolution with one, two, and four channels.
These data converters are ideal for applications where power is limitedsuch as in Universal Serial Bus (USB)-powered instruments, including oscilloscopeswhere a personal computer (PC) provides the power, the graphical user interface (GUI), and the display screen. In USB applications, USB 2.0 allows as much as 2.5 W power to be drawn from a PC and USB 3.0 allows as much as 4.5 W power to be drawn from the PC. Because of their low-power operation, the HMCAD1510 and HMCAD1511 are both well suited for USB-powered applications. The power consumption of the HMCAD1511 can be configured via SPI bus, allowing an instrument like an oscilloscope to trade off between power and performance. When operating at only 570 mW, the performance of the HMCAD1511 is degraded by less than 2 dB. The table provides a quick performance summary of all three data converters.
The data converters share various other features that make them ideal for oscilloscopes and other portable instruments. For example, their use of integrated crosspoint switch (CPS) arrays provide both cost and printed-circuit-board (PCB) area savings compared to the use of discrete CPS designs. The HMCAD1510, HMCAD1511, and HMCAD1520 ADCs boast pipeline architectures, which by nature is switches, allowing the CPS to be synchronized with the ADC. Such synchronization offers several advantages over a discrete CPS implementation:
1. The synchronized CPS is implemented as an extension to the sampling switch. There is no noise contributed by the CPS, since the pipeline ADC sampling noise is solely defined by the sampling capacitor.
2. The CPS is located within the ADC, with a short distance to the sampling capacitor and no need for impedance matching between the CPS and ADC.
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These ADCs are also well conceived in terms of thermal design. In higher-power ADCs, dissipated power can increase the local temperature of a circuit so that device lifetime is reduced. But the 29C/W thermal resistance of the HMCAD1511 package gives a 21C on-chip over-temperature at 1 GSamples/s. This thermal resistance is well accounted for during development of the ADC, with no lifetime reduction expected for operation over the full industrial temperature range and no additional cooling devices required.
These pipeline ADC cores are time interleaved to achieve the high sampling rates. The interleaving clock tree is optimized to ensure that a set of interleaved ADC cores will be equivalent of one ADC operating at the sum of ADC core sample rates. The number of ADC cores available for interleaving depends on the number of channels. In single-channel mode, all internal ADC cores are interleaved to achieve the maximum sample rate. In dual-channel mode, the number of ADC cores available for each channel, and the sampling rate, is divided by two. To avoid changing the clock input frequency, the internal clock divider can be used to compensate for the changed sample rate; this is also valid for quad-channel mode. Both the CPS array and the internal clock tree will automatically adjust according to the chosen number of channels (Fig. 2).
When utilizing time interleaving, mismatches between the ADC cores, called time interleave artifacts, can limit performance. To maintain high performance, the HMCAD1510, HMCAD1511, and HMCAD1520 ADCs control interleaving time skew to only 2.5 ps RMS. In most 8-b, 1-GSamples/s systems, no calibration will be required for such a low time skew. Oscilloscopes designed for low cost often rely on external time interleaving, with a field-programmable gate array (FPGA) or complex programmable logic device (CPLD) to generate the interleaving clock tree. The time skew in these systems can exceed 100 ps root mean square (RMS), requiring tradeoffs between degraded performance or increased cost to develop complex calibration algorithms. Internal interleaving eliminates the tradeoff, and saves board space (Fig. 3).
Two or four HMCAD1511 ADCs can be used as building blocks to achieve operation at sampling rates to 4 GSamples/s. This is done by generating a time-interleaving clock tree on the PCB on which the converters are mounted. To 4 GSamples/s, this can be done with PCB layout techniques, and no CPLD will be required. In addition, multiple HMCAD1520 ADCs can be used to achieve a similar purpose, since this converter includes an 8-b HMCAD1511 mode. Figure 4 shows how the HMCAD1520 is configured via the SPI bus.
In high-speed modes, time interleaving artifacts can limit the dynamic range of HMCAD1520 to 60 dB, requiring calibration for increased dynamic range. To avoid this issue, HMCAD1520 offers a quad-channel 14-b precision mode to 105 MSamples/s. In precision mode, the HMCAD1520 operates as a true intermediate-frequency (IF) ADC with as much as 85-dB linearity, ideally suited for use in spectrum analyzers. The CPS array is available in precision mode and can be used for resolution scaling to 16 b. This is done by assigning all CPSs to one analog input and adding the four 14-b channels in an FPGA to create a single 16-b ADC channel (Fig. 5).
A high-performance phase-lock loop (PLL) is required with the HMCAD1520 to take advantage of its low clock jitter and achieve high SNR performance. For example, the model HMC830LP6CE fractional-N PLL with integrated voltage-controlled oscillator (VCO) from Hittite Microwave is suitable for driving the clock input of the HMCAD1520. The combination yields below 200 fs jitter, preserving SNR performance at high input frequencies.
To explore the capabilities of the HMCAD1520, HMCAD1511, and HMCAD1510 ADCs, the EasySuite evaluation kit is available, which includes ADC configuration and analysis. It is based on motherboards equipped with standard FPGAs from Xilinx. EasyStack FPGA firmware is available in EasySuite and covers data transport, memory controller, and digital oscilloscope triggers. Samples and evaluation kits for the HMCAD1520, HMCAD1511, and HMCAD1510 ADCs are currently available from stock.