By using three different semiconductor processes, a three-chip design can be optimized for individual amplifier and attenuator functions to achieve outstanding overall VGA performance.
Variable-gain amplifiers (VGAs) help control amplitude levels in cellular transceivers while simplifying system design. Essentially, they replace at least two components: an amplifier and a voltage-variable attenuator (VVA). In the case of the model MAAM-009320 VGA from M/A-COM Technology Solutions, the goal was to develop a VGA with sufficient bandwidth to cover all cellular frequency bands, including Long Term Evolution (LTE). The result is a three-chip solution housed within a single 4 x 4 mm QFN package that handles 400 to 2700 MHz. The package holds a GaAs pseudomorphic high-electron-mobility-transistor (pHEMT) amplifier, MESFET voltage-variable attenuator (VVA) with 0 to 3 V analog control, and a GaAs heterojunction-bipolar-transistor (HBT) amplifier with high input-third-order-intercept (IIP3) performance.
The three-chip VGA achieves +40 dBm minimum output IP3 with only 231 mA current and +5 VDC bias voltage, outstanding performance for cellular applications from 400 to 2700 MHz. A multi-chip approach to a multifunction component can be a superior solution compared to a single chip solution because it allows the use of different wafer processes to optimize the performance of each function.The MAAM-009320 VGA was designed to operate with analog control and cover all cellular frequency bands. It was also designed to deliver a wide attenuation range with outstanding linearity and low DC power consumption. A QFN package was set as a requirement because these are commonly used, have good thermal paths, and have large available die sizes relative to the package sizes. The MAAM-009320 replaces a driver amplifier and VVA with a single part. It balances linearity and noise figure using an amplifier-attenuator-amplifier approach.
Combining these three component functions within a single monolithic-microwave integrated circuit (MMIC) can reduce the size of the solution compared to individual circuits. Still, using a single semiconductor process for three different component functions can lead to compromises in performance. The challenge in designing this VGA was to select a process that would deliver good amplifier linearity for the third stage; good VVA linearity for the second stage; and a reasonable combination of noise figure, linearity, and impedance match for the first stage. Because such a process was not available, three different processes were chosen. Table 1 and Table 2 provide chain analyses of the amplifier: VVA-amplifier lineup for cases of maximum gain and 25-dB attenuation, respectively. Since linearity is a key parameter, the design starts with the third stage, then works back to the second and first.
A 2-m HBT process was selected for the third stage since it had the best amplifier linearity in this frequency range for a given DC power consumption. The design for the driver amplifier was already available in the form of M/A-COM's model MAAM-009286, used in cellular communications applications. The MAAM-009286 amplifier die met all the third-stage requirements without the need for a new MMIC design. The MAAM-009286 has 15.5 dB gain and +42 dBm output IP3 at 2140 MHz when biased at +5 VDC and 155 mA. The amplifier chip requires five external passive components to set impedance matching for the frequency band for optimal return losses, gain, and IP3. This MMIC is a single-ended design with gain that slopes negatively with frequency, yet still provides enough gain to deliver 20-dB small-signal gain even at the high-end frequency of 2700 MHz.
The 1-m GaAs MESFET process from M/A-COM was used to design and fabricate the analog VVA die since this process would meet the linearity requirements for the variable attenuator. Most semiconductor processes can produce attenuators with input IP3 levels of greater than +40 dBm in their on (Vgs = 0 V) and off (pinched-off) states. However, the input IP3 for an analog attenuator varies with gate-source voltage, Vgs, and can suffer large dips near the pinchoff region. This 1-m MESFET process has a pinchoff voltage of -2 VDC and yields excellent linearity for analog attenuator circuits.
The VVA design features a pi configuration (Fig. 1). Triple-gate field-effect transistors (FETs) are used to improve linearity. The shunt arms have absorptive resistors to present reasonable loads to the amplifiers over the control voltage range. The two series FETs each use resistors between the drains and sources to set flat maximum attenuation versus frequency. The gate peripheries are 1.26 mm for each of the shunt FETs and 1.8 mm for each of the series FETs. Feedforward capacitors on all FETs improve linearity near the pinchoff regions of the FETs.
M/A-COM's 0.5-m power GaAs pHEMT process was chosen for the first-stage amplifier, since the goals of this stage were to provide enough gain to meet the overall VGA gain requirement, with a wideband match with minimal matching components, reasonable noise figure, and high enough IP3 to not impact the output IP3 of the overall VGA. This first-stage amplifier is a self-biased design with feedback for wide bandwidth. This stage's 600-m transistor was biased at +5 VDC and 83 mA (Class A operation) for maximum linearity (an output IP3 of +36 dBm).
Figure 2 shows a basic circuit schematic diagram of the first stage amplifier. Parallel feedback is provided by a resistor with a DC blocking capacitor. A shunt 640-Ω resistor is used to ground the gate while minimizing die area and providing some stability. A series inductor is used to improve the input match. An external DC blocking capacitor is used on the input port to minimize die area. An external RF choke was also used with its value chosen to set the performance at 400 MHz. The DC blocking capacitor on the output must be on the die in order to bond directly to the attenuator die and isolate the voltages on the amplifier and attenuator. The on-chip capacitor values are in the range of 8 to 10 pF to minimize die area while meeting the minimum frequency requirement of 400 MHz.
All performance goals were met at 2140 MHz, including the primary goals of 24 dB minimum gain, +40 dBm minimum output IP3, and 25 dB minimum attenuation. Table 3 provides a summary of the design's performance. Data is also provided at the frequency limits demonstrating solid performance over the full design range of 400 to 2700 MHz. The gain slopes with frequency because the output stage is a singled-ended design. The first and second stages have relatively flat S21 responses between 400 and 2700 MHz. The attenuation range also slopes somewhat due to the parasitic capacitances of the FETs. The bias conditions at all frequencies were +5 VDC on the input and output stages, +3 VDC on the VVA supply line, and 0 to +3 VDC on the VVA control line, with 231 mA total bias current.
Table 3 shows the HBT amplifier's performance at the band edges. The WCDTMA2100 band of 2110 to 2170 MHz was chosen for extensive evaluation because it is a common cellular test band near the upper edge of the frequency range. Losses due to the test circuit board were not removed from these results since those losses are relatively low at 2140 MHz, about 0.2 dB per transition. At the maximum gain state, the small-signal gain was 25.6 dB. Figure 3 shows the gain versus control voltage at 2140 MHz. The gain at the maximum attenuation state is -0.8 dB, resulting in an attenuation range of 26.4 dB.
For noise figure, the application calls for a requirement of 5 dB at the maximum gain state, while the measured performance for the VGA revealed noise figure of about 3 dB. As the control voltage increases, the VVA attenuation increases, increasing the overall noise figure as well. The noise figure increases to 4 dB at 5 dB attenuation, 12 dB at 15 dB attenuation, and 18 dB at 25 dB attenuation.
As Fig. 4 shows, the output IP3 at the maximum gain state is +42 dBm, similar to that of the output stage if used in a single-function configuration. This shows the negligible effects of the first two stages on output IP3 performance. All output IP3 data were measured with levels of +9 dBm per test tone, with the output stage matched for optimum IP3 performance.
At the minimum gain state, the input IP3 is +16 dBm. The input IP3 varies with control voltage, following the trend predicted in nonlinear computer-aided-engineering (CAE) simulation models. As the shunt FETs move just out of the pinchoff region, there is a dip in input IP3 as shown in Fig. 5 at a 0.5 V control voltage. Another dip occurs at a 2.5 V control voltage when the series FET begins to enter the pinchoff region. These dips were successfully minimized in the final design.
The output power at 1 dB compression matches the performance of the output stage of +28 dBm. Because the gain of the output stage is 15.5 dB, the output power at 1 dB compression (P1dB) of the attenuator is +30 dBm, and the output P1dB of the first stage is +20 dBm, the output stage dominates the contribution to output P1dB in the maximum gain state. The input P1dB at the maximum gain state is +2.5 dBm, increasing to +6 dBm at 5 dB attenuation, +7 dBm at 15 dB attenuation, and +7.5 dBm at 25 dB attenuation.
The input return loss did dip below 10 dB towards the middle of the control voltage range; this was due to the impedances of the VVA changing with control voltage. The impedances of the series and shunt FETs vary to present a reasonable (but not perfect) match at all control voltages. A shunt 3.9-nH inductor was placed at the input of the VGA to improve the input return loss over the full control voltage range. Figure 6 shows the resulting input return loss over the control voltage range, while Fig. 7 shows the output return loss.
In summary, the MAAM-00320 VGA successfully meets the design goals of high gain, high linearity, and low current consumption over the full design frequency range of 400 to 2700 MHz.
M/A-COM Technology Solutions
100 Chelmsford St.
Lowell, MA 01851