Both handset and infrastructure developers are asking for higher levels of integration and creative ways to preserve performance while cutting costs and speeding time to market.
Integration has been a key to the advancement of wireless communications, leading to smaller devices with more functionality. Although the mobile handset is at the forefront of these trends, cost savings and time to market are among the drivers pushing for higher integration in cellular infrastructure as well. As wireless integrators strive for more functions in smaller packages, the trend in ICs continues toward higher levels of analog, digital, and high-frequency integration in a single device. To complicate matters, both handset and infrastructure integrators are trying to fit multiple wireless standards in one system. To balance these various demands, creative design techniques are leveraging advanced technology resources and expertise in amplifiers, transceivers, and other devices to create more highly integrated systems that do not sacrifice performance.
Dale Wilson, Analog Devices' Senior Marketing Manager, RF Group, states, "Size is an obvious consideration and most important in handheld or portable applications but also desired in larger systems, where customers want more processing capability in a given volume. In many instances, customers expect a system cost reduction as multiple functions are incorporated in a single device. There is also the reduced cost of assembly and test as well as actual design work. If all of the tuning, filtering, biasing, etc. is handled on the chip, there is less work required to be done by the user. This can also improve the customer's time to market. Performance of discrete RF components will generally be better than that of a more integrated device. But in many applications, good enough' performance is acceptableas long as price targets are achieved. As analog and high-performance RF devices make more use of CMOS processes, there are more opportunities to incorporate digital control functions as well."
To handle such increased levels of integration, ADI has traditionally implemented many of its high-performance RF products in advanced bipolar processes. Customers then apply digital control functions within their systems. Wilson points out that newer BiCMOS processes are now being used, which have superior analog performance and the additional capability to integrate digital control functions on chip. CMOS processes also are being utilized for highly integrated RF devices, often using digital processing to overcome RF performance limitations.
This past fall, the firm debuted RF mixers and modulators that enable high-density radio cards while increasing capacity and speed for Long Term Evolution (LTE) and fourth-generation (4G) base stations (Fig. 1). The ADRF660x series of mixers and ADRF670x series of modulators combine multiple discrete functional blocks into a single device. The four ADRF660x products integrate an active RF mixer, RF input balun for singleended 50- input, and a PLL synthesizer with integrated voltage-controlled oscillator (VCO) in one package. The active mixer provides a voltage conversion gain of 6 dB. The differential IF output operates to 500 MHz. The ADRF6601 receive mixer operates from 300 to 2500 MHz with an internal LO range of 750 to 1160 MHz. It reaches 1-dB compression with +12 dBm input power and achieves an input third-order intercept point of +30 dBm. The mixer exhibits 12 dB single-sideband (SSB) noise.
Each of the four ADRF670x modulators integrates an analog in-phase/ quadrature (I/Q) modulator, RF output switch, and phase-locked-loop (PLL) with integrated VCO in a single RFIC. The modulator input bandwidth is 500 MHz. The ADRF6701 I/Q modulator's PLL/synthesizer uses a fractional-N PLL to feed a multiplied-by-two version of the LO signal to the I/Q modulator. The PLL reference input accepts signals from 12 to 160 MHz. The modulator covers an output frequency of 400 to 1300 MHz. It boasts an internal LO frequency range of 750 to 1160 MHz. The device provides +14 dBm output power at 1-dB compression and +29 dBm output third-order intercept point. It offers a noise floor of -158 dBm/Hz.
PAs FEEL THE SQUEEZE
As 3G wireless networks are completed and a transition is being made to 4G systems, the use of distributed architectures and active antenna systems is driving the need for smaller and more efficient transceiver and PA implementations. For example, the MAX9947 from Maxim Integrated Products promises to simplify the implementation of Antenna Interface Standards Group (AISG)-compliant base stations and tower-mounted equipment (Fig. 2). The single-chip transceiver packs a transmitter, receiver, and active filters into a 3-x-3-mm TQFN package.
The transmitter includes an OOK modulator, a bandpass filter that is compliant with the AISG spectrum-emission profile, and an output amplifier. The receiver includes a bandpass filter with 200-kHz bandwidth centered at 2.176 MHz center frequency. It also includes an OOK demodulator and a comparator for reconstructing the digital signal. The MAX9947 offers input dynamic range from -15 to +5 dBm at 50 . Its resistor-adjustable output power, which spans +7 to +12 dBm, compensates for losses in external circuitry and cabling. The transceiver supports all AISG data rates: 9.6, 38.4, and 115.2 kb/s.
On the PA side, designers are faced with high peak-to-average ratios and stringent spectral-growth specifications. Scintera Networks, Inc. is hoping to provide an answer with the SC1887 adaptive RF PA linearizer (RFPAL) system-on-a-chip (SoC), which performs complex signal processing in the RF domain. The SC1887, which is fabricated in standard CMOS, implements the firm's Gigahertz Signal Processing technology (GSP). This programmable analog-signal-processor (ASP) platform vows to provide the advantages of digital signal processing (DSP) at the reduced power and size of analog solutions. The SC1887 RF in and RF out solution supports modular PA designs that are independent of the baseband and transceiver subsystems. Consuming less than 600 mW, the SC1887 is well suited for lower-power transmitters. The SoC covers 698 to 1000 or 1800 to 2800 MHz. It supports an input signal bandwidth to 60 MHz with a peak-to-average ratio of 10 dB. The chip promises to provide an adjacent-channel-leakage-ratio (ACLR) improvement to 26 dB.
Enhanced efficiency also is the driver of a PA development from Nujira and RF Micro Devices, Inc. The firms assert that wireless-infrastructure vendors will be able to leverage this PA to develop a single multimode, broadband RF front end that can be deployed to meet various transmission standards anywhere in the world. The PA design, which targets 4G base stations, integrates RFMD's RFG1M09180 180-W gallium-nitride (GaN) broadband power transistor with Nujira's Coolteq.h envelope-tracking power modulators. Using just one RFG1M device with a Coolteq.h module, the RFMD Nujira RF front end transmits over a 728-to-960- MHz band. It delivers average output power of +45 dBm with over 50 percent efficiency. Using GaN devices currently in development at RFMD, the two companies expect to cover cellular frequencies from 700 to 2600 MHz with just three broadband PAs.
By using carbon nanotubes as heatdissipation material in PA transistors, Fujitsu Laboratories Ltd. has successfully operated highfrequency, 100-W-class, flip-chip amplifiers that also target the mobile base stations designed for 4G systems. To achieve high frequency, output, and amplification, the firm developed "dual-side heat-dissipation" technology, in which heat is dissipated through both sides of the transistor chip. According to the company, this technology also enables the reduction of the transistor chip size to less than two-thirds the size of existing transistor chips.
Using the flip-chip structure, carbonnanotube bumps were run between the electrode on the top of the amplifier and the substrate. In addition, a heatsink was affixed to the reverse side of the amplifier to draw heat away from the amplifier from both its front and back sides. To attain high amplification rates at high frequencies, the interconnects need to be at least 10 m long. Fujitsu used an aluminum-iron (Al-Fe) film to grow carbon nanotubes to a length of 20 m or longer perpendicular to the board. The new technology promises to improve heat dissipation by an increase of 1.5X compared to conventional methods.
This work underscores the concern of many mobile-communications design engineers for effective thermal management. According to Homayoun Ghani, Toshiba America Electronic Components' Development Manager, Microwave, RF, and Small Signal Devices, higherefficiency designs require a smaller heatsink, which enables the use of smaller and lighter devices in mobile-systems applications. He notes, "The resulting challenges are mainly the heat generated from these small devices and how to properly design a system capable of handling that heat." Ghani points out that some systems integrators are using liquidcooling techniques.
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Cellular handsets provide their own set of integration obstacles. According to Shane Smith, TriQuint's Senior Director for Marketing, Mobile Devices, "For analog integration, semiconductor companies are developing power amplifiers that deliver multi-mode, multiband operation. Today, five bands of WCDMA with EDGE and GMSK modulation requires our customers to purchase six PAs. In 2010-2011, customers will be able to purchase one PA module with the same functionality."
To target 3G/4G converged handset architectures, TriQuint Semiconductor provides the TriQuint unified Mobile Front-end architecture (TRIUMF; Fig. 3). The module provides an RF footprint that combines GSM, EDGE, WCDMA, and HSPA transmit functionality. In doing so, it promises to offer up to a 50-percent size reduction over standard multiband module solutions. By combining four separate PA modules into one, TRIUMF cuts handset assembly cost. It also miniaturizes the RF system, as a single converged PA module coupled with antenna switching, mode/ band, switch and duplexers will reduce front-end board area.
Although CMOS offers many compelling benefits in terms of cost-effective integration, CMOS PAs simply have not been able to match or surpass the performance of gallium-arsenide (GaAs) PAs in handsets. Patrick Morgan, Javelin Semiconductor's Vice President of Marketing, explains, "Axiom Microdevices developed a 2G PA architecture based on the distributed active transformer (DAT), which is a primarily analog technique. ACCO Semiconductor developed a new transistor technology for PAs called MASMOS. In summary, companies attempting to solve the CMOS PA challenge have followed three paths: digital signal processing, aggressive analog architecture derivations, or making significant process changes to the standard CMOS flow."
The JAV5001 PA from Javelin, which targets W-CDMA and HSPA wireless communications, is implemented in a standard CMOS process. This PA houses the transceiver together with the baseband. In a 3-x-3-mm package, the JAV5001 integrates circuitry for power regulation, PA bias, input and output matching, and power control. The PA operates on a single voltage supply. During W-CDMA modulation, it boasts linear output power to +28.0 dBm. The PA exhibits gain ranging from 5 dB in low-power mode to 27 dB in high-power mode. It provides an electro-static-discharge (ESD) HBM rating of 2.5 kV. Its adjacent channel leakage ratio (ACLR) is typically -40 dBc with a maximum of -38 dBc with a 5-MHz offset. The JAV5001 offers 40 percent power-added efficiency (PAE) in high-power mode and 28 percent PAE in medium-power mode. It features maximum noise of -150 dBm/Hz from 2400 to 2484 MHz to -147 dBm/Hz in the RX band with a 190-MHz offset.
As more high-frequency functions are handled or assisted by digital circuitry, the biggest obstacle is probably to maintain analog performance. As stated by Ramesh Ramchandani, Director, Marketing & Business Development at TowerJazz, "IC designers driving a true integration of both digital and analog functions onto a single chip are finding it increasingly difficult to get the performance out of their integrated chip as they would out of an analog chip. Many engineers are getting creative in finding circuit solutions to compromise for the lack of analog performance. However, one of the drawbacks here is the extra circuitry that must be included that can require additional capacitors, resistors, inductors, and other passive elements to bring the performance to par." The decades-old quandary still thrives: Integration is sorely needed, but it cannot be gained at the price of even a little performance