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In the industrial arena, Echelon is pioneering communications SoCs so that the building industry can offer automation services with a united hardware standard. Its multi-protocol, ISO-FT 6050 SoC can support both the LonWorks and BACnet protocols over IP. With that SoC, the company hopes to enable building automation devices that promote the Industrial Internet of Things (IIoT). At the AHR Expo this January in New York, N.Y., OEM device customers of Echelon demonstrated products built around the framework for smart controls. Current-generation FT 6050 devices operate with digital communications. Yet future expansion to wireless topologies is possible, thanks to the enhanced integration capability of SoCs.

With all of the highly integrated digital, analog, and RF electronics that go into a modern SoC, engineers increasingly need electronic-design-automation (EDA) software and hardware test tools to simulate and test these complex devices. Developing SoCs is an in-depth process of designing, simulating, verifying, manufacturing, and testing a complex system with many core components in a very dense space. In the past, discrete chips were used for each of the core functions. With heightened integration, however, most of the core components are on the same die or within the same package. These integration steps add cost savings, reliability, yield, and time savings to the manufacturing process.

The extent of integration in modern SoCs also adds new development challenges. Some of the roadblocks in developing software for these designs are the computational power necessary to simulate a device with billions of transistors and billions of states, which operate in the analog, digital, and RF domain. Designing software to handle all of the complex realms of operation and iterations of the design process is an additional problem. Some companies provide an in-house design suite that is optimized for their particular process. Present solutions, like Microsemi’s Libero SoC, offer a complete SoC design suite for the firm’s field-programmable-gate-array (FPGA) product lines. Additionally, companies like Algotochip offer code-to-chip services for the digital domain. Because there is not a wide selection of complete and generic RF SoC design-to-test tools available, engineers must use a variety of different EDA tools in a design-flow process.

Cadence Virtouso, Agilent Technologies GoldenGate, Mentor Graphics HyperLynx, AWR Microwave Office, Synopsys HSPICE, and Ansys DesignerRF all offer RF circuit simulation software with electromagnetic (EM) simulation engines. Other available tools that could aid the in the RF-SoC design process for simulation verification are MATLAB/SIMULINK, Spice, Verilog-AMS, VHDL-AMS, and SystemC. While some SoC designs are on a monolithic substrate, others consist of stacked die or packages. A design suite and EM simulator with 3D capability could be required for multi-dimensional designs. Reasonable consideration should be applied when deciding on a design flow with several software tools, as the optimization of the calibration and interfacing between the design tools could save cost and time in the design process.

The RF devices of even a few years ago comprised discrete components with externalized RF test ports. This allowed for relatively straightforward software verification and bench-level testing. RF SoCs are making the testing environment more complicated, as the real estate for test points on an IC could be limited. Complex packaging could lead to further complications. Often, probe stations are required for IC-level testing. Testing highly integrated devices in a manufacturing environment could slow down operational test, as the number of states skyrockets with device performance.

A proposed solution to RF SoC testing challenges is to use the internal technology available within the SoC to automate self-test operations. This would enable the built-in processors and sensor to run complex testing routines for functional self-test. Additional circuits could be added for pass/fail qualification testing internal to the chip. Although such an approach would increase the design complexity of the RF SoC, it has the potential to eliminate many testing steps during the verification and manufacturing stages. It could even prevent repetitive and costly quality-control checks.

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