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During a recent company visit with HYPRES Chief Executive Officer Richard Hitt, the difference in integration level with the new process became apparent: from digital circuits with as many as 12,000 Josephson junctions fabricated with the legacy four-layer process to circuits with more than 75,000 Josephson junctions now possible with the new six-layer process. “We needed to put more Josephson junctions on our chips,” notes Hitt, “but with the four-layer process, we were quickly exhausting our capabilities.”

The dividends of more wiring levels available in the new six-layer process will be compounded by the increase in critical current density or Jc - the key parameter defining the switching speed of Josephson junctions. HYPRES legacy four-layer process has typical critical current density of 4.5 kA/cm2. The new process is showing the capability to reach Jc levels of 10, 20 kA/cm2 or greater.

Perhaps more importantly, the new process supports fabrication of superconducting wafers with multiple Jc levels, so that ICs can be further optimized for required functionality. As Hitt points out, “We have unveiled six layers, but we plan to go beyond and do more layers down the road. A greater number of layers translates into greater functional complexity.”

Many customers for superconducting circuits are interested in increased dynamic range of RF receivers, whether in the commercial or military sectors, in order to find and isolate a desired signal amidst a large amount of interference. The superconducting circuits have been proven to provide high dynamic range in wide bandwidth. “We were stuck at four layers for quite some time,” Hitt recalls, “and the four-layer process required that we use thicker and thicker material, with the stress increasing with the thicker layers.” A critical point in creating the new six-layer superconducting process was developing planarization steps that could support reliable viaholes and throughholes between the multiple layers.

The new process is based on pure niobium, rather than on niobium alloy materials. “We started with a planarization technique developed in Japan where we etch back on the metal on a chip before each chemical mechanical planarization step,” Mukhanov says. “They do it layer by layer, where we have developed it further by doing this as a kind of ripple process. We don’t want to have pattern-dependent polishing rates, but want to achieve a more uniform polishing of patterns on the chip.”

 Mukhanov mentions that the company is also experimenting with some new materials, notably for the development of high-speed ferromagnetic memory for direct integration with their digital and DSP circuits.

Superconducting technology is not for everyone, since it requires maintaining the required (cooler) operating conditions, and thus is not suitable for handheld units. But the company is quite supportive of those wishing to design superconductive circuits and provides its design rules for download on the HYPRES website.

In support of its new fabrication capabilities, HYPRES features a full suite of software design tools, including XIC from Whiteley Research and AutoCAD from AUTODESK. Also included are electrical simulation packages such as Spectre® from Cadence, PSCAN, Microwave Office from AWR Corp., and the Sonnet Suites electromagnetic (EM) simulation software from Sonnet Software. The firm also boasts extensive in-house high-speed analog and digital test equipment and quality-assurance (QA) inspection equipment to back its superconducting foundry services.

HYPRES, Inc., 175 Clearbrook Rd., Elmsford, NY 10523; (914) 592-1190, FAX: (914) 347-2239.

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