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In addition, owing to the bulk-injection technique, the parasitic capacitance between the RF and LO stages—which significantly degrades the conversion gain at a high frequency—is eliminated without a matching LC network. Therefore, a widely flat conversion gain can be achieved across the entire bandwidth. Since the LO signal is injected into the bulk of the core transistor M2, the threshold voltage can be manipulated by the LO signal at the body terminal. Typically the threshold voltage of an n-channel MOSFET is given by Eq. 121:

VTH (LO) = VTO + r([2|φF| - VBS(LO)]0.5 - [2|φF|]0.5   (1)

where:

VBS = the source-to-bulk potential difference;

VTO = the threshold voltage for VBS = 0;

r = the body-effect coefficient; and

φF = the Fermi potential with a typical value in the range of 0.3 to 0.4 VDC.22

From Eq. 1, it can be seen that the threshold voltage VTH (LO) of the transistor is a function of the voltage between the bulk and source, VBS, and the device M2 is switched on and off alternately as the LO signal is in the positive or negative phase of the LO. Hence, the mixing function is achieved by the LO signal, which modulates the threshold voltage of transistor M2.

On the other hand, the mixer core is similar to a common-source degeneration structure in a low-noise amplifier (LNA), where transistor M1 not only acts as the tail current source but also as a degeneration resistor to improve the linearity of the mixer. The high output impedance of PMOS transistor M3 is used as an active load to transfer current to voltage for the IF output signal. Moreover, the forward bias voltage VB is employed at the body of M1 to meet the low-voltage-supply design.

Design A Low-Voltage UWB CMOS Mixer, Fig. 2

To suppress the noise influence of the following blocks and reduce the requirement for the gain of LNA, the UWB mixer should exhibit reasonable conversion gain. Based on the schematic diagram of Fig. 1(b), Fig. 2 shows the small-signal equivalent circuit of the bulk-injection mixer core. Assuming that the gate-drain parasitic capacitance, Cgd,  along with body effects are ignored, the small-signal voltage gain, AV, can be solved by means of Eq. 2:

AV =vIF/vRF= -(gm/rop)/[1 + (rop/ r0) + (ron/ r0) + gm ron]   (2)

where:

r0  = the channel resistance; 

ron = the output resistance of transistor M1; and

rop = the output resistance of transistor M3;

gm = the transconductance of NMOS transistor  M2.

Assuming that the local oscillator (LO) signal is an ideal square wave, and the RF signal is mixed with the LO signal and modulated as the desired output frequency, fRF - fLO, where fRF and fLO represent the RF and LO frequencies, the proposed mixer’s conversion gain (CG) can be expressed as Eq. 3:

CG = (-2/π) {gm rop/[1 + (rop/ r0) + (ron/ r0) + gm ron]}   (3)

In practical circuit design, r0 ≈ ron, gmron ≈ 1 + rop/r0, and the expression for conversion gain can be simplified as Eq. 4:

CG ≈ (2/π)(rop/ron)   (4)

From Eq. 4, it can be seen that the conversion gain of the mixer is determined solely by the output resistance of transistors M1 and M3. To achieve high conversion gain with minimum power consumption, the small-gate-width size device M3 is selected to increase the output resistance, and it also should be biased in its active region. This suggests that increases in resistance rop will boost CG to an arbitrarily high value, which is not correct. Since the voltage drop across the active load M3 is proportional to the output resistance, a large value of rop results in a low voltage between the drain and source of bulk-driven stage M2.

The above-assumed condition no longer holds as it is indicated in Eq. 4 when the low output resistance, r0, of transistor M2 is considered, which degrades the conversion gain of the mixer. Another approach for optimum conversion gain is to reduce the output resistance of M1, but at a cost of circuit linearity and power consumption. Therefore, a design tradeoff exists between conversion gain and linearity for the proposed mixer topology.

A mixer must have acceptable linearity to suppress interference and maintain high sensitivity. In a multiple-standard wideband receiver, in-band and out-of-band interference signals can result in severe blocking, cross-modulation, and intermodulation—all challenging to the linearity of the mixer. For low-power applications, a major design challenge is to achieve the required circuit linearity under limited bias conditions. A number of approaches are available for realizing a high-linearity mixer, but limited power schemes discourage additional active circuit implementations.

The post-distortion technique is one such approach available to Gilbert-type mixers.23 The quest to realize high linearity with little DC current consumption has motivated the source degeneration common-source configuration shown in Fig. 1(a). The linearity of this approach can be understood by means of a mathematical analysis, assuming that bulk-injection stage M2 is operated in its active region as it is turned on. Equate current flow through device M2 and rop in Fig. 1(b):

(VDD – vIF)/rop = βn {VG + vRF - [(VDD - vIF)/rop]ron - VTH}2   (5)

βn = (1/2)μnCox(W/L)2   (6)

where:

βn = the transconductance parameter and Cox = the gate oxide capacitance per unit area.

As indicated in ref. 14, the IIP3 can be expressed as:

IIP3 (dBm) = 10log(8c) (7)

c ≈ (1/2βn2)[4βn(VG - vTH)]2 x [{4βn(VG - VTH)ron + 1}0.5 + 1]   (8)

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