This application note concisely presents recommendations for engineers designing a PCB for mounting SMD terminations, attenuators, and resistors.
For high-power, surface-mount resistive products, power-handling capability is affected by printed-circuit-board (PCB) design. The assembly process also may pose problems. To help engineers better understand these issues and how to mitigate their effects, Anaren offers an application note titled, “Power Handling Considerations for SMD Terminations, Attenuators and Resistors.”
The seven-page document focuses on three sections: PCB design, solder-joint quality, and thermal-via quantity. In the first section, a system is shown in which the PCB will have the highest thermal resistance. Here, the board design has the most significant impact on the system’s power-handling capabilities. An equation is provided for power/thermal analysis, showing how the PCB’s total thermal resistance is the reciprocal sum of the thermal resistances of the dielectric material, via plating, and via fill material.
An equation also is provided to calculate thermal resistance due to thermal conductivity. Because the dielectric material for most PCBs has a much lower thermal conductivity than its copper conductors or solder, the thermal resistance of the dielectric is very high while the reciprocal is near zero. This section moves on to providing tips, such as ensuring that all thermal vias are solder-filled to reduce the PCB’s overall thermal resistance. Increasing copper-plating thickness or decreasing PCB height also will decrease the thermal resistance of the vias. In addition, raising the cross-sectional area of the thermal vias will decrease thermal resistance. It should be noted, however, that the number of thermal viaholes that can fit underneath the ground pad depends on the viahole diameter.
The section on solder-joint quality notes that all of the power dissipated in the SMD component must pass through solder before reaching the heatsink. Thus, a poor-quality solder joint can reduce the part’s power-handling capability. The note advises that solder joints be 0.002 to 0.003 in. in height and have 20% or lower void voltage. The discussion on thermal viahole quantity emphasizes that the way that thermal viaholes are arranged can impact the number of viaholes that will fit in the allotted area. Two layouts are shown that maximize the number of viaholes. In closing, this application note concisely presents recommendations for engineers designing a PCB for mounting SMD terminations, attenuators, and resistors.
Anaren, Inc., 6635 Kirkville Rd., E. Syracuse, NY 13057; (315) 432-8909.