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Simulated output power and CL

As the studies show, a number of conclusions can be drawn. For one, the input reflector networks have been used to both impedance-match the fundamental-frequency signals and short-circuit the second- and fourth-harmonic signals. The output reflector networks are used to both impedance-match the fourth-harmonic signals and open-circuit the second- and sixth-harmonic signals. As shown in Fig. 5 and Table 2, the quadrupler’s specific layout can be obtained by analysis of these matching requirements.

Table 2

By using commercial analysis software such as ADS, it is also possible to determine the output power (based on an input-power level) and the CL curves for a frequency-multiplier design. From such computer simulation curves, the maximum output power point and minimum CL point for the quadrupler is found to be near 87 GHz when the input power is around +20 dBm. The minimum CL is around 13 dB and the output power is around +7 dBm. This quadrupler design was realized with a 0.1-μm-gate-length GaAs pHEMT process, with the quadruplier chip, which measures 0.8× 1.6 mm, shown in Fig. 6.

Fabricated quadrupler

The device was testing in a Class 10,000 cleanroom, measured on wafer using a model M150 probe station from Cascade Microtech, a model ACP110-S ground-signal-ground (GSG) W-band probe from Cascade Microtech, and a model W8486A W-band power probe from Agilent Technologies. Simulated and measured results are compared in Fig. 7, showing that the output frequency characteristics between modeled and measured results are somewhat offset. This is most likely because the Schottky diode model may not be totally accurate, since the quadrupler works at W-band frequencies. In addition, because of the fabrication precision and dielectric losses, differences may exist between the simulated results and the actual measurements. 

Comparing performance and frequency

Still, it was possible to simulate the performance of a Schottky diode multiplier from 80 to 100 GHz with results that were fairly close to the measurements of an actual fabricated quadrupler for that same frequency range. The analysis showed that it is possible to reduce the multiplier’s CL, provided that the input-power network and the input/output reflector networks are fully optimized. The monolithic quadrupler that was finally fabricated can produce output levels of about -3 to +2 dBm across the target frequency range of 80 to 100 GHz.

Yong Fang, Doctor

Hai Zhang, Doctor

National Key Laboratory of Science and Technology on Vacuum Electronics, School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu (610054), People’s Republic of China; e-mail: fangyongguestc@gmail.com

Baoqing Zeng, Professor

National Key Laboratory of Science and Technology on Vacuum Electronics, School of Physical Electronics, University of Electronic Science and Technology of China, Chengdu (610054), People’s Republic of China

Department of Electronic Engineering, University of Electronic Science and Technology of China Zhongshan Institute, Zhongshan (528402), People’s Republic of China

Tiguo Gan, Professor

10th Institute of China Electronic Technology Group Corporation, Chengdu (610036), People’s Republic of China

Ye Yuan, Doctor

School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu (610054), People’s Republic of China; e-mail: Yuanyeacdefk@163.com

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