Samir Kameche, Mohammed Feham, and Mohammed Kameche

Frequency synthesizers based on phase-locked loops (PLLs) are widely used in radio communications systems. Such signal sources are known for their high frequency resolution and fast switching speed, while maintaining good frequency accuracy over time and changing temperatures. Of course, some communications systems have specific requirements in terms of performance, and it is sometimes necessary to optimize the performance of a frequency synthesizer for a particular parameter. As will be shown in Part 1 of this two-part article, it is possible to design a PLL frequency synthesizer for fast switching speed or low spurious noise, with those two parameters representing a tradeoff that depends upon the synthesizer’s loop filter. By properly designing the loop filter, a desired balance can be achieved between PLL spurious levels and lock time.

Many wireless communications systems require a frequency synthesizer that can combine low-noise operation and high frequency resolution with short locking time.1 Many systems require optimization of synthesizer locking time and reference spurious levels.2,3 It is possible to design a PLL that is optimized for different performance parameters, often by trading off one or more of its performance parameters to improve another. Figure 1 shows a conventional PLL frequency synthesizer.4 It has been used for a variety of applications, including as a control oscillator for wireless transmitters and receivers and as a timing element for digital equipment. It consists of a high-stability crystal oscillator, phase detector, charge pump, lowpass filter (LPF), voltage-controlled oscillator (VCO), and programmable frequency dividers.

In the PLL frequency synthesizer, the phase/frequency detector (PFD) compares a fed-back frequency with a divided-down version of the reference frequency from the crystal oscillator. In an integer PLL frequency synthesizer, outputs are divided by integers. When a phase or time difference between the PFD’s outputs is detected, the charge-pump circuit converts the difference into a voltage. The loop filter extracts the DC component of this voltage, which is then used to drive an external VCO to increase or decrease the output frequency and drive the average output of the PFD to zero.

In the PLL synthesizer, the input reference divider reduces the required reference input frequency, while the feedback divider reduces the output frequency required for comparison with the scaled reference frequency. The loop filter is a critical component in a PLL synthesizer, linking the VCO with the PFD. Because PFDs and VCOs can be somewhat more limited in their designs, it is the design of the loop filter that affords the main flexibility in determining a PLL’s bandwidth. Although an active filter could be used, a passive filter is generally more desirable for practical applications. 5,6

Figure 2 shows a linear mathematical model representing the phase of the PLL in its locked state, 4 where Kf is the phase-detector/charge-pump gain (in mA/rad), S is the phase-detector gain factor, Z(s) is the transfer function of the loop filter, N is the main divider ratio, and KVCO is the gain of the VCO (in MHz/V). The phase of the oscillator to be stabilized, φ0, is compared with the phase of the reference, φr, and adjusted until the difference is driven to zero. The phases represented by φi and φe are the initial and error phases, respectively, of the oscillator to be stabilized.

In Fig. 2, the output is modeled as a phase rather than a frequency, which makes more sense considering the phase detector works in terms of phase rather than frequency. The VCO gain is multiplied by a factor of 1/s to convert it from a frequency to a phase. The PLL phase transfer functions are as follows.

The forward-loop gain can be shown as:

The reverse loop gain can be found from:

The open-loop gain can be found from Eq. 3:

By combining these transfer functions, the closed-loop gain can be found:

Figure 3 shows the circuit for a second-order passive loop filter. Its transfer function, Z(s), can be found from:

The time constants, T1 and T2, which determine the pole and zero frequencies of the filter transfer function, are defined by Eqs. 6 and 7:

T2 = R2 . C2          (7)

Thus, the third-order PLL open-loop gain can be calculated in terms of the frequency, ω; the filter time constants, T1 and T2; and the design constants, Kf, KVCO, and N:

The phase of the open-loop gain as a function of frequency depends upon the single pole and zero of the transfer function:

By setting the derivative of the phase margin equal to zero, as in Eq. 10:

the frequency point corresponding to the phase inflection point can be found in terms of the filter time constants, T1 and T2. This relationship is given by Eq. 11:

The values of the filter time constants, T1 and T2, can be found from Eqs. 12 and 13:

The component values for the filter can be found from T1 and T2 and the loop bandwidth by applying Eqs. 14-16:

 

Current switching noise in the dividers and the charge pump, at the reference frequency rate, FREF, may cause unwanted frequency modulation (FM) sidebands at the RF output of the synthesizer. In a wireless communications system, the phase-detector comparison frequency is generally a multiple of the RF channel spacing. These spurious sidebands can cause noise in adjacent channels. Additional filtering of the reference spurs is often necessary, depending upon the width of the loop filter. This is often the case in modern time-division-multiple-access (TDMA) digital cellular communications systems, such as GSM cellular systems.3

A recommended filter configuration in such a case is the third-order filter shown in Fig. 4.4 The attenuation added from its use is found from Eq. 17:

The resulting third-order filter has a time constant for the added lowpass section, T3, that can be found from Eq. 18:

T3 = R3 . C3          (18)

The transfer function of the loop filter in Fig. 4 is given by Eq. 19:

where Z(s) is the transfer function for the second-order loop filter given by Eq. 5. The cutoff frequency of the new filter, ωc, can be found from Eq. 20. Capacitor C1 can be expressed by means of Eq. 21.

Similar to what was done for the second-order filter, the component values can be found from Eqs. 22 and 23:

For the loop filter in Fig. 4, it is necessary to calculate the voltage noise present at the output ports of resistors R2 and R3. The equivalent root-mean-square (RMS) noise voltage generated by the resistance can be found7 by applying Eq. 24:

where:

k = Boltzmann’s constant;
T0 = the device temperature (in°K);
B = the bandwidth (in Hz); and
R = the resistance (in O).

Figure 5 and Figure 6 offer schematic-diagram noise models for resistances R2 and R3, respectively, as being equivalent sources of noise voltage appearing in series with each resistance. The derivation of the real noise voltage versus input frequency at the tuning port of the PLL synthesizer’s voltage-controlled oscillator (VCO) is based on the basic circuit using the models of Fig. 5 and Fig. 6.4

Reference spurious products are also introduced in the simulation. The power levels of these can be calculated by the closed-loop transfer function evaluated at the spurious offset frequencies, Fspur. In general, spurious products are a result of either signal leakage or the impedance mismatch of the charge pump. In several studies, Fspur is assumed to be a multiple of the comparison frequency, Fcomp. The power level of the reference spurious products can be found by applying Eq. 258:

In general, narrower loop bandwidths result in lower reference spurious levels but in longer frequency lock times.

The loop bandwidth, the most critical system design parameter for a PLL, is determined by many factors, and is usually external to a PLL chip. A PLL user typical chooses a loop bandwidth and will design the PLL circuits for this parameter. As mentioned earlier, the classical design tradeoff in a PLL is lock time versus spurious performance. The spurious performance may look better for a narrower loop bandwidth, but the lock time is longer. For a large loop bandwidth, the lock time may be faster, but the spurious levels will increase.

To better understand the dynamics of a loop filter in a frequency synthesizer, a precise evaluation was undertaken to ensure the precision of the PLL frequency synthesizer design. Figures 7, 8, 9, and 10 show the output spectra and transient responses for previous cases of the loop filter. For the PLL frequency synthesizer, the settling time for a frequency step of 25 MHz is about 240 µs with a loop bandwidth of 10 kHz.

Figure 11 shows the impact of comparison frequency on the lock time for a PLL frequency synthesizer with 10-kHz loop bandwidth. The performance was simulated by switching the synthesizer’s frequency between F1 = 890 MHz and F2 = 915 MHz. The comparison frequency was changed, but the loop filter was recalculated in each case to maintain a constant loop bandwidth (ωp = 10 kHz). When the comparison frequency is less than 20 times the loop bandwidth, the lock time obtained (about 240 µs) meets the requirements of most modern communications systems. However, when the comparison frequency is 1 MHz, the rise time of the synthesizer is greatly increased, which in turn increases the lock time. In the case where the comparison frequency, Fcomp, is 2 MHz, the lock time becomes more degraded.

Editor's Note: The second part of this article will appear in the May issue of Microwaves & RF.

References

  1. G. Singh Patel and S. Sharma, “Comparative Study of PLL, DDS, and DDS-based PLL Synthesis Techniques for Communication System,” International Journal of Electronics Engineering, Vol. 2, No. 1, 2010, pp. 35-40.
  2. David Vye, “Performing Transient Analysis on PLL Frequency Synthesizers,” Microwave Journal, Vol. 45, No. 1, January 2002, pp. 62-79.
  3. William O. Keese, “An Analysis and Performance Evaluation of a Passive Filter Design Technique for Charge-pump PLLs,’’ Application Note AN-1001, July 2001, National Semiconductor, Santa Clara, CA, 2006, www.national.com.
  4. S. Kameche, M. Feham, and M. Kameche, “PLL Synthesizer Tunes DCS 1800 Band,’’ Microwaves & RF, Vol. 46, No. 6, June 2007, pp. 84-90.
  5. S. Kameche, M. Feham, and M. Kameche, “Simulating and Designing a PLL Frequency Synthesizer for GSM Communications,” High Frequency Electronics, Vol. 7, No. 12, December 2008, pp. 36-41.
  6. Jun Lee, “Phase Locked Loop Systems Design for Wireless Infrastructure Applications,” Microwave Journal, Vol. 53, No. 5, May 2010, p. 74.
  7. L. Lascari, “Accurate Phase Noise Prediction in PLL Synthesizers,” Applied Microwave and Wireless, Vol. 12, No. 2, 2000, pp. 30-38.
  8. D. Banarjee, PLL Performance, Simulation, and Design, 4th ed., National Semiconductor, Santa Clara, CA, 2006, www.national.com.