Guo Xiaorong, Jingru Sun, Chunhua Wang, and Chao Yuan

Radio-frequency identification (RFID) is a versatile wireless technology for tracking and identifying items over short distances. It has advanced a great deal in recent years due to the availability of low-cost integrated-circuit (IC) solutions, with RFID transmitters/receivers shrinking in size and dropping in price. The reading/writing range of a RFID system mainly depends on the choice of operating frequency, the radiated power from the reader, the sensitivity of the tag, the data rate, and various other factors.1 Compared with near-field RFID systems, such as 125 kHz or 13.56 MHz, which are limited by the short communication distance and low data rate, an ultra-high-frequency (UHF) RFID system has the advantages of a longer communication distance and a higher data rate.2,3 More and more researchers are reporting on projects to develop mobile UHF RFID reader transmitters. In the current report,4 a 900-MHz CMOS RFID transmitter front-end was realized for a fully integrated CMOS UHF RFID reader for use from 860 to 960 MHz in support of the EPCglobal Class-1, Generation-2, and ISO-18000-6A/B/C standards. The transmitter consists of an frequency upconversion mixer and linear power amplifier (PA). The upconversion mixer provides 5.5 dB power gain and input third-order-intercept point (IIP3) of 12 dB. The PA exhibits an output power of +21 dBm and power-added efficiency of 32%. The RF transmitter front-end is integrated with an on-chip CMOS PA, with output power of +20.5 dBm and IIP3 of +11.5 dBm.

In conventional RFID receiver designs for UHF applications, in-phase (I) and quadrature (Q) baseband signals processed by programmable gain amplifiers (PGAs) are frequency upconverted by means of mixers and 900-MHz local-oscillator (LO) signals. The power dissipation of such circuitry is low, but the linearity is lacking for effective RFID applications. Some proposed RFID transmitter circuits employ off-chip inductors to improve the efficiency, but these are not easy to integrate in many circuits.5,6 In refs. 7 and 8, two fully integrated transmitters were proposed, although the output power of those designs was relatively low.

As an alternative to these other approaches for a higher-power, higher-linearity UHF RFID integrated transmitter/reader system, a novel CMOS transmitter front-end was proposed in ref. 9. The transmitter consists of an active frequency upconversion mixer, two buffer amplifiers, a linear PA, a nonlinear PA, and digital control units. The linear PA was used to boost the amplitude-shift-keying (ASK) modulated RF signals, while the nonlinear PA served to boost the unmodulated carrier. Unfortunately, in this solution, the output power of this circuit is relatively low and the supply voltage is fairly large.9

To overcome the limitations of the other RFID approaches, a new fully integrated CMOS RF transmitter front-end is proposed. It consists of a frequency upconversion mixer and a PA. In the mixer, a complementary transconductance current injection technique improves circuit linearity and reduces noise. The PA must have high efficiency, but implementing high efficiency in standard CMOS is not trivial due to the low breakdown voltage. For high efficiency and power, self-biased cascade techniques were employed in the PA. All of the inductors required for the RFID transmitter circuit were integrated on the CMOS chip, which includes the power amplifier with +20.5 dBm output power at 1-dB compression and input third-order-intercept point of +11.5 dBm. Compared to earlier work4-9, this RFID transmitter front-end offers enhanced performance in terms of output power, power-added efficiency (PAE), linearity, and supply voltage.

Figure 1 shows a block diagram for a typical mobile RFID reader transceiver. The RF transmitter proposed in this article employs a zero-intermediate-frequency (zero-IF) configuration, using only a mixer and power amplifier. In the transmitter, modulated digital baseband signals are converted to analog ASK baseband signals by means of a digital-to-analog converter (DAC). Then, the mixer upconverts the baseband signals to the desired RF signal frequency. The proposed upconverter mixer can be used across a wide range of frequencies for use with different local oscillator (LO) frequencies. Output RF signals from the mixer are boosted to levels required by the RFID antenna by the power amplifier.

The upconversion mixer is designed to upconvert lower-frequency baseband signals directly across a range of 860 to 960 MHz. This mixer (Fig. 2) features high linearity, high gain, and low noise, and can operate in different frequency ranges. It employes a complementary transconductance current injection technique. As shown in Fig. 2, transistors M3 and M4 are complementary transconductance devices.

The upconversion mixer derives from a conventional Gilbert-cell-based double-balanced mixer structure. Transistors M1, M 3, M2, and M4 serve as the complementary transconductance stages. The complementary gain (CG) of the mixer circuit can calculated by Eq. 110:

As these relationships show, the transconductance gain will be increased compared with the transconductance stage of a single metal-oxide-semiconductor (MOS) transistor. The noise figure of a conventional Gilbert-cell mixer circuit can be found from Eq. 2. The noise figure of the same can be found by applyling Eq. 3.

Compared to a conventional Gilbert-cell mixer, the noise figure of the new design will be less. The input third-order-intercept (IIP3) point of a Gilbert-cell mixer can be found from Eq. 4, while the IIP3 point of the proposed mixer is given by Eq. 5:

Compared to a conventional Gilbert-cell mixer, the IIP3 of the new configuration will be higher. From Fig. 2, it is known that a fully differential circuit would effectively suppress harmonics.10

The last part of the RFID transmitter to consider is the power amplifier. Its purpose is to provide sufficient RF power to drive the antenna for transmission of a signal. Because of the low breakdown voltage of standard CMOS, implementing an integrated and efficient power amplifier by means of a silicon CMOS process presents a challenge. When the output power in the PA circuit reaches a maximum level, the drain voltages of transistors M7 and M8 are two to three times the drain voltage, VDD, and the gate-drain voltage will exceed the process breakdown voltage under normal conditions. For that reason, self-biasing techniques are used in the common-gate structure to overcome the limitations of a process with low breakdown voltage. With a self-biased circuit, it is possible to adjust the gate voltage of the common-gate transistor so that the gate-drain voltage does not exceed the breakdown voltage, while at the same time the drain voltage is kept constant.11Figure 3 shows a schematic depiction of the proposed CMOS PA for the RFID transmitter, with a small-signal equivalent circuit shown in Fig. 4.

The overall voltage gain of the power amplifier can be found from Eq. 6:

A = A1 * A2 * A3(6)

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The voltage gain of the first part of the circuit is calculated by using Eq. 7 and Eq. 8.

The voltage gain of the second part of the amplifier can be found by applying Eqs. 9 and 10:

The voltage gain of final section of the power amplifier circuit can be found by using Eq. 11:

The output power of the amplifier circuit can be expressed by Eq. 12:

where:

Vin = the input voltage and
Rload = the load resistor.

The PAE of the amplifier circuit can be expressed as Eq. 13:

where amplitude A can be increased by adjusting the circuit device value. As Eq. 13 indicates, output power and PAE will improve as A is increased.

To understand the behavior of the proposed RFID transmitter front end, the circuit was simulated and fabricated in a standard 0.18-m silicon CMOS semiconductor process. Figure 5 shows the layout of a fabricated circuit. Figures 6(a), 6(b), and 6(c) show mixer output-versus-input characteristics for different signal levels. From 860 to 960 MHz, the mixer's IIP3 is between +10.92 and +12.45 dBm; the noise figure (Fig. 7) is between 8.88 and 9.12 dB.

Figure 8(a) shows the output power for the power amplifier at 860, 900, and 960 MHz, while Fig. 8(b) shows the PAE at the same three test frequencies. In referring back to the input/output-power relationships shown in Fig. 6, the output power was +20.50 dBm with PAE of 28% for an input power level of 0 dBm. The maximum output powe for the power amplifier is +21 dBm, while the maximum PAE is 32%.

Figure 9 shows the output voltage waveform of the RFID transmitter as a function of time. It is clear from this plot that the output voltage exceeds 4 V, with the transmit output power reaching about +20.5 dBm when the input signal is 0 dBm.

The two tables provide additional information on the RFID CMOS transmitter. Table 1 offers a summary of the simulated results for the circuit, separated by mixer and power amplifier. Table 2 provides a comparison of this new transmitter front-end design with other published results. Over its operating range of 860 to 960 MHz, this new transmitter circuit achieves higher output power and improved linearity over the earlier efforts. MWRF

Acknowledgments

This work was supported by the Science and Technology Key Project of Changsha (No. K0902012-11) and Science and Technology Project of Hunan Province (No. 2010GK3052).

References

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  3. ISO-IEC_CD 18000-6C, Version 2.1 c2, July (2005).
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