Jinjiang Liu, Chunhua Wang, Xiadong Cao, and Jun Xu

Current-mode signal-processing techniques offer some advantages compared to voltage-mode techniques. Some of these advantages include increased linearity, simpler circuits, wider bandwidth, lower power consumption, and simple implementation of basic signal operations, such as addition and subtraction.1 As a result, numerous active elements have been developed for current-mode use,2,3 such as a current conveyor, current operational amplifiers (COAs), operational transconductance amplifiers (OTRAs), and current differencing buffered amplifiers (CDBAs).

A CDBA can be constructed in a number of ways, provided that the current-mode components have been introduced. The benefits of using a CDBA in a signal-processing application include its high slew rate, freedom from parasitic capacitance, wide bandwidth, and relatively simple implementation. For example, the circuit in ref. 3 employed two commercial current-feedback amplifiers (CFAs), such as the model AD844 from Analog Devices, where the CFAs functioned as second-generation current conveyors and voltage buffers.

In this CDBA design, however, the CDBA characteristics were dominated by the CFA properties. In ref. 4, a design approach included bipolar-junction-transistor (BJT) technology, based on a current subtractor and voltage buffer amplifier. In ref. 5, the circuit was designed for implementation in silicon CMOS technology with the CDBA consisting of a differential current-controlled current source (DCCCS) followed by a voltage buffer. However, the operating frequency of this CDBA was under 1 MHz, and the terminal voltage (Vp, Vn) caused by the parasitic resistance can not be neglected compared to voltage Vz.

The technique in ref. 6 exploited improved active-feedback cascade current mirrors to obtain the high impedances at the output terminals as well as high accuracy of the current transfer ratio. But that design was also limited in bandwidth, at 37 MHz, and required a high supply voltage (about ±5 V). To overcome the high supply voltage, the author in ref. 7 employed a flipped voltage follower (FVF) technique to reduce the voltage as low as ±0.6 V. But again, the bandwidth was limited (about 25 MHz). To overcome the high-frequency limitations of PMOS transistors, the CDBA of ref. 8 was designed such that the signal has an all NMOS signal path, and this design achieved a 3-dB bandwidth as wide as 500 MHz. This CDBA circuit also enjoys good voltage and current gain accuracies, and low resistance at both the current-input terminals (p, n) and the output-voltage terminal (w). Still, it suffers from high power consumption.

The current report focuses on designing a high-performance CDBA using all NMOS mirrors, with a current subtraction circuit and a voltage follower, and using only a few transistors. The current subtraction circuit exploits a low-voltage current mirror followed by an improved Wilson mirror to decrease the supply voltage and increase the bandwidth, respectively.

Compared with other design work, this proposed CDBA offers a wider dynamic range and lower resistance at both current input (p and n) terminals. It also operates with lower supply voltage and power consumption than the designs of refs. 5, 6, and 8.

Figure 1(a) shows the proposed CDBA circuit, where p and n are input terminals and w and z are output terminals. It is equivalent to the circuit of Fig. 1(b), which uses dependent current and voltage sources. The current and voltage characteristics of the CDBA can be described by Eq. 1:

According to this matrix and the equivalent circuit of Fig. 1(b), a CDBA can be considered as a transimpedance amplifier (TIA) that converts the difference of the input currents Ip and In at terminals p and n, and hence Vz is named as the current output, respectively; the voltage of the w terminal follows the voltage of the z terminal. The input terminals, through which Ip and In flow, are internally grounded. Finally, it can be further inferred that the terminal impedances of the p and n terminals must be very low. A CDBA of this design can be implemented with bipolar and CMOS technologies.

Figure 2 provides a schematic diagram of the proposed CDBA circuit. It employs all NMOS mirrors, and also contains the current subtraction circuit and the voltage follower. The current subtraction circuit provides the difference currents Ip and In, which flow into the current subtraction circuit through its low-impedance inputs (p, n) and lead away from the high-impedance terminal z. The z terminal is internally connected to the input of the voltage follower. The voltage, induced on an external impedance, connected with the z terminal, is copied to the low-impedance w terminal of the follower output.

The current subtraction circuit is formed by transistors M1 through M10. The circuit exploits the flipped voltage follower current sensor (FVFCS). The FVFCS has been used in the past for different applications, including as part of a power amplifier. For example, the first and simplest use of the FVFCS is as the input stage of a low-voltage current mirror.9-14 High-performance current mirrors with low input and output voltage requirements are needed as building blocks in mixed-mode very-large-scale-integration (VLSI) systems that operate from a single supply of 1.5 V or less. High accuracy requires very high output resistance and low input resistance.

The basic implementation of a FVFCS is given in Fig. 3, which has the lowest input resistance—as well as the lowest input voltage requirements—reported to date. The input voltage required for such current mirror is in the order of Vds, which can be as small as 0.1 V, which is much smaller than the gate-source voltage (Vgs) drop required for a conventional low-voltage current mirror.

The input impedance is very low, on the order of 10 to 50 O, and can be expressed by Eq. 2:

rin = 1/(gm1gm2rol)          (2)

The minimum voltage supply for the FVFCS can be found by Eq. 3:

VDDmin = |VTN + 2VDS          (3)

From this, it can be seen that the mirror in Fig. 3 operates with a low voltage supply and low power consumption.

A high-performance current mirror also requires high output resistance and low voltage requirements at the output stage. A simple approach for realizing the output stage is by means of a simple or cascade current source. Normally, two of the low-voltage current mirror circuits can be used to accept input currents Ip and In. Then, the differential current between Ip and In can be achieved by the use of an improved Wilson mirror, constituted by NMOS transistors (Fig. 4).

More specifically, it is well known that a Wilson current mirror or an improved Wilson current mirror (Fig. 4) have better high-frequency behavior than a cascade current mirror without loss of the highoutput impedance and low static error features (having equal advantages with respect to the simple current mirror).1 Moreover, the improved Wilson mirror also provides an increase in the output resistance, as shown by Eq. 4:

For this reason:

gm2 = gmb2, rds2 + rds4 = rds2 rds4 gm2

and:

ro = rds2 gm2 rds4          (5)

Consequently, the output impedance of a Wilson mirror is more than just a simple mirror.

The output stage of the proposed CDBA is based on the voltage follower. And the voltage follower also formed by a basic mirror and a Wilson mirror (Fig. 5). The impedance at mode w is very low and its voltage can be expressed by Eq. 6:

with:

νw = ßvνz          (7)

and:

 

where Rw is the resistor connected to |terminal w, if:

gm1rob = 1

and:

gm2(1 + gm3rob/2) = gw

then:

νw ˜ νz.

The CDBA was designed for integrated-circuit (IC) fabrication in a CMOS process. It was simulated by PSPICE time-domain software based on a 0.18-µm CMOS process.

The aspect ratios of the current subtraction circuit elements (devices M1 through M10) are W/L = (30 µm)/(1 µm), and the voltage follower (devices M11 through M15) have an aspect ratio of W/L = (10 µm)/(1 µm). The supply voltages used are +VDD = -VSS = 0.8 V, and the constant bias current (Ib) of 30 µA was realized by employing basic current mirrors.

Figure 6 shows that the impedance of terminals p and n are equal to 12 Ω for a wide frequency range. It can be seen from Fig. 7 that terminal w has an impedance of 46 Ω. Figure 8 shows the variation of z terminal impedance with frequency, which yields an impedance of 276 kΩ.

The device characteristics given in Fig. 9 indicate that the CDBA circuit provides good performance and good potential for use in analog circuits. It has high linearity and accuracy over a wide dynamic range. As Fig. 9(a) shows, the maximum offset current on terminal z is equal to 0.23 µA. Figure 9(b) shows that the output voltage, Vw, follows voltage Vz. The power consumption for the CDBA circuit is 0.43 mW for Ip = In = 0 µA and 0.48 mW for Ip = In = 30 µA.

Figure 10 shows the CDBA’s transfer characteristics. The current and voltage transfer ratios, ap, an, and ßv, were found to be 1.020, 1.020, and 0.988, respectively. The 3-dB frequencies for Iz/Ip, Iz/In, and Vw/Vz are approximately 376, 376, and 726 MHz, respectively. Table 1 summarizes the simulation results for the CDBA.

CDBA-based circuits offer excellent terminal characteristics and high common-mode rejection ratios for a variety of applications, including in oscillators,16 integrators,1 to simulate active inductance,17,18 for proportion integration differentiation,19 and for multiplier/divider circuits.20 CDBAs have also been applied in continuous-time current-mode filters such as single-input multi-output filters,6 multifunction filters, high-order filters,2,3 and universal filters. As an example, a five-order RLC Chebyshev lowpass filter was designed using CDBAs, grounded resistors, and capacitors. Figure 11 shows a current-mode, fifth-order RLC passive ladder prototype, and a CDBA-based normalized filter.

The fifth-order current transfer function can be expressed by Eq. 9:

where:

Iin = the input current and

Iout = the output current.

The numerator is a polynomial with positive and negative real coefficients. In this filter, VDD = VSS = ±0.8 V; resistors RS = RL = R = 500 Ω; and capacitors C1 = C5 = 2.48 pF and C2 = C3 = C4 = 1.22 pF. Figure 12 shows the simulated amplitude response for the fifth-order CDBA-based lowpass filter. Based on the numerical simulations, a cutoff frequency, fc, of 120 MHz was determined for this filter. As the simulations show, its passband response exhibits excellent amplitude flatness.

Table 2.

Acknowledgment

The authors would like to thank the Open Fund Project of the Key Laboratory at Hunan University for financially supporting this research under grant No. 10K016.

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