Digital technology improves as precision photolithography continues to deliver more transistors per given chip area. And with the improvements come greater impact on RF and microwave designs. High-speed analog-to-digital converters (ADCs), for example, have paved the way for software-definedradio (SDR) architectures that are being adopted in everything from cellular base stations to military tactical radios. And thanks to high-performance digital-to-analog converters (DACs), complex waveforms can be generated with high precision and wide dynamic range.

ADCs and DACs are among the most diversified of electronic components in terms of performance. Specifiers can choose from a wide range of capabilities as defined by clock rate, frequency range, bit resolution, noise levels, power consumption, and dynamic range. Products range from converters with 24-b resolution at lower frequencies for audio applications and lower-resolution, lower-frequency converters for control applications to high-resolution, high-performance converters for medical, military, and wireless communications applications. One basic tradeoff is in precision versus frequency: as the desired frequency range reaches higher, the available bit resolution is lower. For example, ADCs and DACs with 24-b resolution are common through 100 kHz, whereas converters operating past 1 GHz typically hit a ceiling of about 16 b for precision.

Ideally, an analog signal entering an ADC and transferred to a DAC with comparable bandwidth and precision would exit the DAC appearing identical to the original signal. But digital components suffer the same physical and manufacturing limitations as their analog cousins, with substrate and conductor signal losses, manufacturing tolerances, and impedance mismatches resulting in some signal degradation as part of the conversion process. In addition, the bit resolution of a converter determines the number of digital states with which to represent an analog signal. In terms of a DAC, a waveform reconstructed from 256 digital states will appear more like the original than one reconstructed from 16 digital states (4 b). But some applications may only require a few digital bits of resolution, and cost is another tradeoff in specifying ADCs and DACs, with increasing bit resolution coming at increasing cost.

A converter's least significant bit (LSB) determines the smallest step into which the peak or full-scale voltage range into the converter can be divided. It is also used as a measurement of a converter's bit accuracy, by means of parameters known as differential nonlinearity (DNL) and integral nonlinearity (INL). An ideal ADC will produce two successive output codes differing by only 1 LSB, for a DNL value of zero. But variations in gain and phase through the converter's circuitry and package result in some deviations in LSB, so that real-world ADCs and DACs suffer some percentage of variation in LSB as measured by the DNL and INL specifications. Application note 641 from Maxim Integrated Products contains a glossary of converter terms, including concise definitions of DNL and INL; in addition, Maxim's application note 283 covers measurement methods for DNL and INL.

With the growing use of portable electronic devices for personal and professional use, converter manufacturers are constantly seeking design strategies to deliver high performance with reduced power consumption. In the case of the model AD9125 from Analog Devices, the solution lies in having two DACs in one package. Ideal for wireless infrastructure applications, such as generating in-phase (I) and quadrature (Q) digital-modulation baseband signal components in cellular base stations, the 16-b converter operates at sampling rates to 1 GSamples/s in support of multicarrier generation at cell sites. The DAC features a flexible CMOS interface (see figure). The output signals from the dual-DAC device can be filtered and fed to analog quadrature modulators (AQMs) and then boosted by a power amplifier (PA) for transmission at the cell site. At 800 MSamples/s, producing an intermediate-frequency output of 70 MHz, the dual DAC achieves a spurious-free dynamic range (SFDR) of -72 dBc. At the same sampling rate, for an output of 100 MHz, the two-tone intermodulation distortion (IMD) is -81 dBc. In terms of accuracy, the AD9125's DNL is typically 2.1 LSB while its INL is typically 3.7 LSB.

Although targeting infrastructure equipment, the AD9125 dual DAC is also designed for low power consumption, consuming only 900 mW when operating at a sampling rate of 500 MSamples/s. The device, which is supplied in a 72-lead LFCSP housing, allows full-scale output current to be programmed from 8.7 to 31.7 mA with load matching from 25 to 50 O for true flexibility.

When two DACs aren't enough, Analog Devices' model ADV7123 incorporates three DACs on one chip and in one package. With maximum sampling rate of 330 MSamples/s and 10-b resolution, it is well suited for video processing. It provides a SFDR of 70 dB at 50 MSamples/s and an output frequency of 1 MHz. It operates from a single +3.3- or +5-VDC supply and provides output current from 2 to 26 mA.

NXP Semiconductors also offers a dual DAC for multicarrier wireless transmitters, its model DAC1405D650. It offers 14-b resolution and maximum sampling rate to 650 MSamples/s. It includes an integrated phase-lock loop (PLL) and onboard 32-b numerically controlled oscillator (NCO) for generation of complex modulation. The adjacent-channel power ratio (ACPR) is -71 dBc when tested with two WCDMA carriers at a sampling rate of 614.4 MSamples/s and producing an output frequency of 96 MHz. The thirdorder IMD at that sampling rate and output frequency is -80 dBc. The dual DAC has an on-chip 1.25-V reference and delivers differential scalable output current from 1.6 to 22.0 mA.

Maxim, Linear Technology, and Texas Instruments also have developed DACs targeting wireless communications applications. Maxim's MAX19693 is a 12-b DAC that operates at sampling rates to 4 GSamples/s to synthesize signals with more than 1.5-GHz bandwidth. It provides four 12-b multiplexed low-voltage differential signaling (LVDS) input ports, each operating to 1 GHz in double data rate (DDR) or quad data rate (QDR) mode to achieve the total 4-GHz rating. The high-speed DAC is supplied in an 11 x 11 mm CSBGA package and consumes 1180 mW at 4 GSamples/s. Linear's models LTC1666, LTC1667, and LTC1668 are DACs with 12-, 14-, and 16-b resolution, respectively, at update rates to 500 MSamples/s. Differential outputs boast SFDR of 87 dB for a 1-MHz output signal. The low-power devices consume only 180 mW from 5-VDC supplies. The model DAC5681 DAC from Texas Instruments operates at update rates to 1 GSamples/s with 16-b resolution using an LVDS input signal format and current output format. Its typical SFDR performance is 81 dB.

For sampling analog signals, many of these same suppliers offer high-performance ADCs capable of digitizing the analog signals found in wireless communications and military tactical communications systems. Recently, National Semiconductor introduced its ADC12D1x00 family of two-channel 12-b ADCs in which the channels can also be interleaved for one channel with sampling speeds to 3.6 GSamples/s (see p. S33 in the Defense Electronics supplement to the June 2010 issue of Microwaves & RF). The ADC line includes model ADC12D1800 with sampling speeds to 3.6 GSamples/s in single-channel interleaved mode, model ADC12D1600, which operates to 3.2 GSamples/s in single-channel mode, and the model ADC12D1000, with 2.0-GSamples/s performance in singlechannel mode.

Among its high-speed ADCs, Linear Technology's model LTC2209 is a 16-b unit that operates to 160 MSamples/s. It achieves a full-scale noise floor of 77.3 dB and 100-dB SFDR with a full-power input bandwidth of 700 MHz. Maxim's MAX109 ADC provides 8-b resolution at sampling rates to 2.2 GSamples/s, with a rated full-power input bandwidth of 2.8 GHz. It can be used with singleended and differential input signals and provides output data in standard LVDS format. Analog Devices' model AD6600 is a dual-channel ADC capable of directly sampling analog IFs to 250 MHz. The highly integrated device includes 1-GHz input amplifiers, wideband 450-MHz track-and-hold (T/H) amplifiers, and an 11-b, 20-MSamples/s ADC, which can be used at its full sampling rate for singlechannel operation, or at 10 MSamples/s for each of two channels.

To learn more about data converters, many companies offer application notes with tutorial information. National Semiconductor, for example, has a 64-page "ABCs of ADCs: Analogto- Digital-Converter Basics" for free download in PDF file format.