DSPs And Data Converters Enable Complex Modulation

Microwave and RF engineers have become more familiar with data converters and digital signal processors (DSPs) in recent years. These components are now mainstays in many wireless systems, making possible the complex filtering and algorithms employed in digital modulation schemes and multichannel communications architectures. In essence, analog-to-digital converters (ADCs) sample analog input signals, digital-to-analog converters (DACs) generate complex modulated waveforms for signal transmission, and DSPs provide the sophisticated filtering and signal manipulation in between the two converter types.

The general trend for ADCs, DACs, and DSPs is one of increased processing power at lower power-consumption levels. The recently introduced (see Microwaves & RF, February 2003, p. 118) TMS320VC5501 and TMS320VC5502 DSPs from Texas Instruments (Dallas, TX, www.ti.com) have dual multiply-and-accumulate (MAC) cores and 300-MHz clock speeds for prices starting at $5. These LQPF-packaged devices consume only 200-mW power during normal operation.

The company also recently announced a series of new processors for Universal Mobile Telecommunications System (UMTS) applications, in accordance with the new Open Mobile Application Processor Interface (OMAPI) standard (which is comprised of a set of software interfaces to the operating system and a set of hardware intefaces defining common application peripheral devices). These OMAPI processors combine a DSP and a high-speed microcontroller on a single chip. Based on a 0.13-µm complementary-metal-oxide-semiconductor (CMOS) process, the OMAP1612 processor, for example, combines the company's TMS320C55x DSP core (capable of operation to 204 MHz) with an ARM926TEJ processor core (also capable of operation to 204 MHz). The OMAP1612 is available with 128 to 256 Mb of stacked mobile double-data-rate (DDR) synchronous-dynamic-random-access memory (SDRAM) to help reduce the size of cellular handsets and Personal Digital Assistants (PDAs) while also lending the processing power for wireless streaming-video and multimedia applications. The OMAP1612 offers a dedicated connection to the company's TNETW1130 wireless-local-area-network (WLAN) processor to simplify the interface with 54-Mb/s WLAN circuitry.

Texas Instruments recently established new standards in terms of processing speed with their 720-MHz models TMS320C6414, TMS320C6415, and TMS320C6416 DSPs. All three devices include 1 MB of on-chip memory with differences in peripheral support and inclusion of coprocessors (such as the integral Viterbi and Turbo coprocessors on the TMS320C6416). These high-speed DSPs are well suited for digital video, imaging, and wireless communications applications. (Note that more information on these three new devices is available by logging directly onto the company's website at www.ti.com/720mhzp.)

One of the earlier developers of DSP technology (as Lucent Technologies), Agere Systems (Allentown, PA, www.agere.com) entered the marketplace for dual-MAC DSPs with its model DSP16411. Operating at maximum clock rates to 285 MHz, the DSP is optimized for use with communications infrastructure equipment. In addition to its enhanced direct-memory-access (DMA) capabilities, the DSP features an on-chip programmable PLL clock synthesizer to eliminate the need for a high-speed clock input. It is designed for use with a single +3.3 VDC.

In addition to Motorola (Phoenix, AZ) as a supplier of DSPs, it should be noted that some suppliers of field-programmable gate arrays (FPGAs), including Altera Corp. (San Jose, CA) and Xilinx, Inc. (San Jose, CA), promote the use of their ICs for DSP functionality. For example, Altera's Stratix line of FPGAs includes the embedded memory, embedded processors, and DSP blocks needed for high-speed DSP. The Stratix devices can provide 16 × 16 multiply operations at 270 MHz, for example.

At the recent Wireless Systems Design Conference & Expo (San Jose, CA), Fujitsu Microelectronics (San Jose, CA) announced their model MB86064 dual 14-b DAC for generation of carrier signals in Global System for Mobile Communications (GSM), wireless-code-division-multiple-access (WCDMA), and UMTS systems (see figure). The 800-MSamples/s device supports the wide channel bandwidths of these emerging wireless systems. Fabricated with a 0.18-µm CMOS process, the presence of two DACs within a common package supports diversity-transmit or dual-transmit applications as well as high-speed test equipment.

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Analog Devices (Wilmington, MA, www.analog.com) also made a strong showing at the Wireless Systems Design Conference & Expo with a number of new ICs. For example, the company recently launched a high-speed ADC as well as a DAC, both nominally for cellular applications. The ADC is the 14-b, 80-MSamples/s model AD9245 that consumes less than 500 mW power from a single +3-VDC supply. Available in a 32-pin chip-scale package (CSP), the ADC is ideal for microcells and picocells requiring low power consumption. The converter operates at 80 MSamples/s and supports input frequencies to 100 MHz. It uses a multistage differential pipelined architecture with output error-correction logic to provide 14-b accuracy over a wide temperature range. It features a signal-to-noise ratio of 72 dB and spurious-free dynamic range (SPDR) of −85 dBc. The converter includes a sample-and-hold (S/H) amplifier with a proprietary input sampling network that can be configured for single-ended or differential operation.

The DAC is the model AD9786, a 16-b, 400 MSamples/s CMOS device that allows synthesis of signals at IFs of 140 MHz and higher. Ideal for multicarrier base stations, the DAC offers a noise floor of −163 dBm/Hz and 2×4×/8× selectable interpolation filters at a data rate of 160 MSamples/s. The DAC achieves IMD performance of better than −80 dBc to 300 MHz and SFDR of −90 dBc at 10 MHz.

For sampling applications at slightly less bit resolution, the firm's model AD12400 ADC offers 12-b resolution at 400 MSamples/s. suitable for both military radars and multichannel communications systems, the ADC achieves a SFDR of −75 dBc at 128 MHz and a SNR of 64 dB at the same carrier frequency. Supplied as a packaged module, the ADC features a transformer-coupled analog input and digital processing to achieve the wide dynamic range.

The company also unveiled several highly integrated solutions for wireless applications, including the models AD6635 and AD6652, multiple-channel radio receiver (Rx) processors. The AD6635, for example, is an eight-channel receive-signal processor (RSP) that is capable of processing as many as four cdma2000 or WCDMA channels or eight narrowband GSM or EDGE carriers simultaneously. It has four reconfigurable 80-MSamples/s RSP input channels and eight independent RSP shared-channel resources. The AD6652 is an integrated radio Rx with dual ADCs and RSPs. It is essentially a mixed-signal IF-to-baseband Rx that directly couples outputs from the dual 12-b ADCs to an on-board quad-channel multimode digital RSP. The company explains the RSP as a numeric preprocessor for a DSP, intended to replace the local oscillator (LO), quadrature mixer, channel-select filter, and data decimation found in a traditional superheterodyne radio architecture.

In terms of pure speed, the MAX108 ADC from Maxim Integrated Products (Sunnyvale, CA) manages 8-b resolution at 1.5 GSamples/s while supporting input bandwidths to 2.2 GHz. Designed for single-ended or differential use, the bipolar device is designed for ±5-VDC supplies and has an effective input signal range of ±250 mV. The company's MAX104 offers the same input bandwidth and 8-b resolution, but at a maximum sampling rate of 1 GSamples/s (see Microwaves & RF, March 1999, p. 128). Both ADCs benefit from a bipolar process capable of fabricating NPN transistors with transition frequencies in excess of 27 GHz.

Recently, the company introduced the MAX5888 DAC for multicarrier cellular base stations (see Microwaves & RF, November 2002, p. 95). Designed to generate as many as four UMTS carriers at bandwidths to 100 MHz, the 16-b DAC features a 500-Msamples/s update rate. The SFDR for the MAX5888 is typically −76 dBc when generating a 40-MHz output signal. The DAC dissipates less than 250 mW from a single +3.3-VDC supply. It provides a signal-to-noise ratio (SNR) of −155 dBc and two-tone IMD of −72 dBc for an 80-MHz output frequency.