Combining diode limiters with surge arresters can provide protection for the sensitive components in radar receivers against transmitter and other high level signals.
Radar limiters are designed to protect the components, mainly in the receiver, from damage due to high-level pulses. Large signals can come from a variety of sources, including the radar's own transmitter and electromagnetic (EM) bombs.1-6 Filtering should be provided for these undesired signals, which may differ from useful signals by power level, polarization, spectrum distribution, and direction of arrival (DOA). This report will review the numerous types of limiters used to eliminate these undesired signals because of their excessive power levels.7-11
In most radar systems, limiters work with other circuits to perform several functions, including with polarizationnonselective reflectors to limit the segment of open space from which undesired signals are received, and polarization-selective radiating elements to eliminate signals not complying with a radar system's design polarization and filters, especially bandstop filters.13
Most studies on protecting receivers with limiters have focused on the use of a single limiter in the receive path (Fig. 1), although this approach does not protect all sensitive components in the receive chain, including duplexer circuits. A practical protection solution should include at least two limiters. The effectiveness of the protection is related to the level of power that leaks to the limiter's output, via flat or spike leakage (Fig. 2). But by using limiters with suitably fast response times, such leakage can be minimized.
The basic limiter used in many radar receivers is the diode limiter, which can be analyzed as an active and passive device.7,10,11 As an example, Fig. 3 shows a three-stage passive PIN diode limiter. The PIN diodes are nonlinear elements controlled exclusively by input signal power. At zero bias, the diode's impedance is greater than 1 kç, dropping as low as 1 ç with forward bias.10 For low-amplitude signals, each diode's impedance has a minimum value, which translated to minimal signal loss but minimal isolation as well. For the time that the diodes make a transition from a maximum to minimum impedance value, limiter output signal decreases according to the amount of isolation8, 12:
I 20log0/2R)> (in dB)
where
n = the number of diodes and
R << Z0 for equivalent serial resistance of the diode.
The power absorbed by each diode, Pabs, normalized to input power, Pin, is12:
Pabs/Pin (4R/n2Z0)
A single-stage diode limiter provides about 20-dB isolation, handling several hundred milliwatts of power without damage.8,11 With a large signal, current through such a limiter in saturation can result in destruction of the diode. To prevent damage in the presence of large signals, multi-stage limiters are used. In a multi-stage limiter, limiting diode D1 has a thicker intrinsic (I) layer than the I layer of a switching diode D3. During the leading edge of a large-amplitude input signal, the impedance of cleanup-stage diode D3 changes first, since the transit time for carriers across the thinner I layer is shorter than for the thicker I layers of diodes D1 and D2. This causes a standing wave, in the plane of D2. This enhancedamplitude signal forces the carriers to flow into the I layer of diode D=v, decreasing the impedance of D2. This change of impedance of first D2 and then D1 into a low-impedance state results in high combined isolation. The level of the power leaking to the limiter output is 2 to 4 dB higher than the cleanup stage threshold level. The typical acceptable power level for the input stage of the receiver is +10 dBm, while the threshold level for the thinnest I layer diode is around +7 dBm.8 As a result, energy leaking from the limiter, especially during a spike, can damage sensitive receive circuits.
For higher-power handling, it might make sense to employ limiters using diodes with higher power-handling capabilities, although the level of flat leakage will increase with such diodes. It is possible to increase the number of diode stages, but this will also increase the signal losses. After being subject to the leading edge of a pulse, and passing from a high to a low impedance, the diode becomes well matched to the transmission line, at which time it may absorb excessive energy, resulting in diode damage.7
By using active bias, these flaws in the protection can be overcome. An active limiter requires a control signal to switch to a limiting state. Actively biased diodes have higher power-handling capability than in the passive case, more quickly achieving a deeper saturation state. The reduction in the level of energy absorbed by the diode also decreases the probability of the diode being destroyed by a large signal. In addition, active biasing makes it possible to achieve a shorter recovery time. Of course, active diodes have limitations as well, offering protection only against signals synchronous with the transmitted pulse, being transparent when the control signal is absent, and providing no protection when the supply voltage is lost or switched off. Because passive limiters are self-activating, they are better suited for protection against a large-signal RF burst.7, 11
Whether synchronous or not with the transmit signal, actively biased limiter diodes can enter a saturated state more quickly than in the passive case only when armed with information about the level of input signal to the limiter. Figure 4 shows a two-stage quasi-active limiter designed for reliable receiver front-end protection. Signals from the input directional coupler are provided (via the amplifier) to the input of the Schottky diode detector. Because the detector must work over a wide dynamic range, it should also be protected by a limiter (such as a one-stage passive diode limiter). The output signal from the detector is compared with a reference in the comparator then used to produce the control (bias) signal for the limiter diodes.14 Once the input signal exceeds a threshold level (which can be lower than for passive diodes), the limiter diodes enter into a saturated state. This limiter circuit protects receiver components circuits against any external or internal signals, remaining operational even when the supply voltage drops out, when the diodes assumed passive operation.
This limiter design was evaluated by measurements, using an HP 83732B signal generator from Agilent Technologies for excitation and modulation signals, generating pulses of approximate rise time r of less than 10 ns (Fig. 5)>. The limiter was tested for a number of input signal parameters (Fig. 6), including peak power (Pmax) of 1 kW, pulse width (t) of 100 s, repetition frequency (fp) of 1 kHz, operating frequency (f0) of 3.5 GHz, and leading edge rise time (tr) of 60 ns.
The limiter was first operating passively (no supply voltage) and tested. A plot of amplitude versus time (Fig. 7) shows a distinct spike from the non-zero diode transition time from a high to a low impedance state. Another negative result of passive operation was damage to some diodes with relatively short exposure time to large signals. Then the limiter was tested with a supply voltage applied (Fig. 8). Even during longer exposure to large signals, no diode damage occurred. With an input rise time of 60 ns, almost no spikes were seen in the time plot, showing that in active operation, the limiter responded well to changes in input signal. The isolation was measured as higher than 40 dB.
Surge arresters rely on an arc discharge in gas to effect protection.15, 16 If the voltage applied to the surge arrester exceeds the spark-over voltage, Us, in a closed hermetic space (Fig. 9), an electric arc is triggered that short circuits arrester electrodes. When the applied voltage decreases to a value less than the spark-over voltage, Ue < Us, the arrester electrodes return to an open-circuit state. The resistance changes from an open-circuit value of 1 GV to less than 1 ç in the short-circuit state. Surge arresters also exhibit some residual voltage in their short-circuit state.
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Surge arresters are characterized by their DC and AC spark-over voltages, Us DC and Us AC, respectively. The Us DC voltage is determined mainly by the gap width between electrodes, the gas type, gas pressure, and the preionization state. The Us AC voltage describes the surge arrester under dynamic conditions, when the highvoltage rise rate, dUi/dT, is higher than the Us DC voltage. Figure 10 shows changes of the spark-over voltage Ui as a function of dUi/dT, with statistical scattering for successive ignitions, Usv, considered. 15
Increases in spark-over voltage as a function of voltage rise rate can restrict the usefulness of a surge arrester as a microwave limiter. Still, a coaxial surge arrester limiter designed with an adequately modified inner conductor provides good impedance matching below the ignition point and improved limiter isolation in the ignition state. This limiter design includes an Epcos A80-C90X surge arrester (with Us DC = 90 V), which is evaluated in Fig. 11 along with a configuration in which the surge arrester is replaced with a metallic cylinder corresponding to a device yielding "ideal ignition" (an arc or residual voltage of 0 V). The circuit was tested through 3.5 GHz. Below the frequency in the short-circuit state, the limiter has at least 12.5 dB isolation in the short-circuit mode, with a nonideal short circuit, the isolation will be less. The limiter was tested in the measurement system used earlier with the input signal parameters used for the diode limiter, except for a rise time of
45 ns and Pmax = 275 kW. This power level corresponds to voltage Umax = 117 V with a 50-V transmission line, being slightly higher than the Us DC = 90 V voltage of the surge arrester being used. The voltage rise rate at the limiter input is about 2 kV/s. According to Fig. 10, such a rise rate corresponds to a spark-over voltage of around 500 V and power Pmax = 5 kW. Despite employing the power source with a significantly less power value of Pmax = 275 kW, the surge arrester ignition and limiting effect took place, showing the usefulness of this approach for RF signals.
Figure 12 shows the surge arrester limiter tested with input signals at Pmax = 275 kW and rise time of 45 ns as well as with Pmax = 1 kW and rise time of 60 ns. In both cases, a distinct spike is visible with characteristic minimum prior to the steady state. Its duration decreases with increased power at the limiter input, from 60 ns for Pmax = 275 kW to 30 ns for Pmax = 1 kW. The spike is also lower at the higher input level (Pmax = 1 kW). This could be due to a faster ignition with the increased RF signal amplitude and rise rate.
For the signal with Pmax = 1 kW, the level of the spike is about 10 dB higher than that occurring in the diode limiter. Attenuation observed in the steady state is about 9 dB, lower than the 12.5 dB for the ideal short circuit (Fig. 12). This owes to the fact that the drop-out of the voltage at the arrester in its ignition state is around 10 to 30 V, instead of 0 V for the ideal short circuit. Testing with the Pmax = 275 kW signal lasted about 15 minutes, with no damage to the surge arrester and little change in its electrical parameters. A longer exposure time with Pmax = 1 kW resulted in a large temperature rise in the surge arrester and slight degradation in limiter isolation.
Unfortunately, leakage power from a surge arrester limiter is too high to maintain safe receiver operation. But by using such a limiter in conjunction with a diode limiter, it may be possible to develop a practical limiting solution that provides reliable radar receiver protection. Figure 13 shows a functional diagram of a hybrid limiter composed of two surge arrester limiters (marked LS1 and LS2) and a diode limiter (marked LD.) The sparkover voltage of the surge arrester limiter (LS1), which is inserted into the transmitreceive path, is to be chosen at the level for no ignition during the transmit signal (e.g., Us DC = 180 V). Placement of the limiter directly after the antenna protects the signal path between the antenna and the receiver, including the transmit-receive duplexer (unlike Fig. 1).
Two limiters in cascade are included in the receive path, a surge arrester limiter (LS2) and a diode limiter (LD). The sparkover voltage of the surge arrester in limiter LS2 is set lower than for the LS1 limiter (e.g., US DC = 90 V), allowing a decrease in the level of power reaching the diode limiter. In most cases, the appearance of an unwanted high-level signal will cause LS2 and LD or LS1 or LD to limit. The first case is when the signal is too weak to trigger ignition in the surge arrester within limiter LP1. Another case corresponds to when the signal leaking to the output of limiter LS1 (attenuated by around 10 dB) is too low to trigger ignition in the surge arrester within limiter LS2. When all three limiters LS1, LS2v, and LD are on, it can be assumed that large-amplitude microwave signals will be present.
To evaluate the hybrid limiter, it was tested with the setup of Fig. 5. A cascade limiter composed of surge arrester limiter LS2 and quasi-active diode limiter LD was evaluated by means of measurements (Fig. 14) in a manner similar to tests run on the diode limiter.
Figure 15 shows the hybrid limiter's output for passive operation. Compared to the diode limiter (Fig. 7), the spike duration is shorter with negligible change in maximum value. The hybrid limiter ensures more efficient limiting of power leakage than a single-diode limiter. In the cascaded limiter, as in the surge arrester limiter, a spike with characteristic minimum precedes the steady state. For quasi-active operation, with diode limiter LD part of the cascade, the limiter output was found to be free of spikes (compare Fig. 16 with Fig. 8). The surge arrester limiter decreases the level of power reaching the diode limiter, disregarding the supply voltage. It increases the diode's chances of surviving high-level signals (and protecting the receiver), especially for a case of voltage drop-out.
PIOTR DYDERSKI Przemyslowy Instytut Telekomunikacji(Telecommunications Research Institute) Poligonowa 30, 04-051 Warszawa, Poland; +48 22 48 65 260, e-mail: Piotr.Dyderski@pit.edu.pl.
Acknowledgments
The author wishes to thank Professor S. Rosloniec for his encouragement to undertake the considered problem and for his many helpful suggestions.
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