Silicon CMOS device technology is widely used in wireless designs for its low-power consumption, good high-frequency performance, and suitability for integration. Conventional RF CMOS circuits usually operate as voltagemode configurations, although highspeed current-mode designs are attractive for their low power consumption, wide bandwidths, and wide dynamic ranges. Both approaches offer advantages, making it desirable to create circuits in which both modes can coexist. A transimpedance amplifier (TIA), which converts current to voltage (using a transfer ratio, k, of V_{OUT}/I_{IN}), can serve as a bridge between the two types of circuits. A high-frequency RF TIA can serve not only as a low-noise amplifier (LNA) with variable gain,^{1,2} but also as a current-mode transmitter. The design presented in this report is a variable-gain 2.4-GHz CMOS TIA that employs a current-reuse stage and a cascade differential stage. By control of the transimpedance feedback resistor of the first stage and the bias current of the second stage, the design provides a 15-dB gain-adjustment range without degrading the input and output impedance match. The amplifier design is based on the 0.18- m silicon CMOS process from Taiwan Semiconductor Manufacturing Company.

* Figure 1* shows a block diagram of a current-mode RF transmitter. A low-level current-mode modulated signal from the current-mode mixer must be amplified before it can be radiated by the antenna. If the receiver is in close proximity, the transmitted modulated signal must be at a low level to prevent saturation of the receiver. If the receiver is at some distance from the transmitter, the transmitted modulated signal must be at a higher level, so that gain control is needed in the transmitter in order to adjust signal levels with the distance between receiver and transmitter. An RF TIA can provide the gain control range to accommodate a wide span of distances between the transmitter and the receiver. Based on a commercial silicon CMOS fabrication process, a combination of current reuse and a cascade structure will be used to construct a variable-gain TIA with noise figure of 1.061 dB and power gain of 18.27 dB at 2.4 GHz, The TIA consumes only 6.38 mA current from a +1.30-V supply.

The proposed TIA (* Fig. 2*) consists of two main stages: one is the current-reuse section with a voltage-current feedback resistance stage, and the second is a cascode differential stage. The current reuse topology is actually a basic transimpedance structure.

^{3}The resistance feedback amplifier can be used to derive the current reuse topology.

*shows the resistance feedback input stage amplifier, with a simplified model for this amplifier shown in*

**Figure 3****. As approximations,**

*Fig. 4**can be used to determine expressions for the gain (Av), noise figure (NF), and input impedance (Zin) as*

**Fig. 4**^{4}:

where

g_{m} = the transconductance of transistor M,

R_{L} = the load resistance, and

R_{F} = the feedback resistance.

In these calculations, the circuit is assumed to be connected to a source generator with an internal impedance of R_{S}.

* Figure 5* shows the current reuse topology. By stacking both NMOS and PMOS transistors, the overall equivalent transconductance is increased from (gm) to (gmN+gmP) for the same biasing current. By removing the load resistance, RL, this configuration can maintain the transistors in their saturation region while operating with a minimum supply voltage, without design tradeoffs.

^{4}In the current-reuse configuration of

*, Eqs. 1-3 remain the same according to the equivalence expressions shown in*

**Fig. 5***.*

**Table 1** In * Fig. 5*, an NMOS transistor replaces the feedback resistance.

*shows a current-reuse topology with variable gain. The current-reuse topology is basically a trans-impedance amplifier; in an ideal transimpedance amplifier, the transimpedance gain and the feedback resistance are almost equivalent. The drain-source resistance (r*

**Figure 6**_{DS}) of the NMOS transistor can be found from

r_{DS} = L/GS V_{T})>

where

K = a transconductance factor,

W = the gate width of the NMOS transistor,

L = the gate length of the NMOS transistor,

V_{GS} = the gate-source voltage of the NMOS transistor, and

V_{T} = the terminal voltage.

As the cascade tuning or control voltage, V_{c}, is varied, resistance r_{DS} will also change; as a result, the feedback resistance is variable and the transimpedance gain is also variable. The cascode structure is widely used in analog circuits, with a differential cascade stage shown in * Fig. 8*. The differential-mode gain of this cascode differential stage is expressed in Eq. 4.

where

g_{m5}, g_{m7}, g_{m6}, and g_{m8} = the transconductances of transistors M_{5}, M_{7}, M_{6}, and M_{8}, and

r_{05}, r_{07}, r_{06}, and r_{08} = the output resistances of transistors M_{5}, M_{7}, M_{6}, and M_{8}.

Equation 4 shows that the gain is proportional to g_{m5}, which is the transconductance of M_{5}, and that Eqs. 5 and 6 hold.

where

K' = a transconductance parameter,

W and L = the gate width and length dimensions, respectively, of transistors M_{5} and M_{7},

I_{D} = the DC drain current of the cascode stage,

? = the channel length modulation parameter of transistors M_{5} and M_{7}, and

V_{ds5} and V_{gs5} = the drainsource and gate-source voltages of transistor M_{5}.

When the control voltage, V_{c}, changes, transconductances g_{m5} and g_{m6} will change as well, inferring that the gain can be controlled by varying the control voltage V_{c}.

The proposed cascode differential low-power, variable-gain TIA was simulated based on the parameters of TSMC's 0.18-m silicon CMOS semiconductor process. The complete schematic diagram of the RF TIA circuit is shown in * Fig. 2*. It consumes 6.38 mW total power at 2.4 GHz when operating with a +1.3-VDC supply.

*Figures 9**, and*

**, 10****show simulation results of the TIA's S-parameters and noise figure when sweeping control voltage VC. The control voltage was varied from 0.5 to 0.7 V to achieve a continuous gain tuning range of 15 dB and noise figure of less than 5 dB. It is important to note that tuning control voltage V**

*11*_{c}had negligible impact on the TIA's S

_{11}performance.

* Figures 12, 13*, and

*show the simulation results when the control voltage, V*

**14**_{c}, is set to 0.7 V. The noise figure was only 1.061 dB while the simulated gain (S21) was 18.27 dB. The simulated values of S

_{11}and S

_{22}were -56.88 dB and -36.99 dB, respectively. This shows that good input and output stage impedance matching has been achieved in the TIA design, while maintaining low noise figure and power consumption.

The computer-aided analysis shows that this lowpower, 2.4-GHz variablegain differential TIA should provide excellent performance when fabricated with a commercial 0.18-m RF CMOS semiconductor process. By employing improved TIA and cascade differential structures, the TIA was able to achieve excellent gain range and noise-figure performance. The simulation results show that with a supply voltage of +1.3 VDC, the TIA consumes only 6.38 mW power while delivering a noise figure of 1.06 dB at 2.4 GHz and power gain of 18.27 dB.

REFERENCES

1. E Sacchi, I. Bietti, F. Gatta, F. Svelto, R. Castello, "A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA," VLSI Circuits, 2000, June 15-17, 2000, Digest of Technical Papers, pp. 94-97.

2. Kuo-Hua Cheng and C. F. Jou, "A novel gain control LNA for 2.4GHz application using 0.18-m CMOS," Circuits and Systems, 48th Midwest Symposium on 7-10, Vol. 2, pp. 1330-1333, 2005.

3. M. Karray, P. Desgreys, Charlot, J.-J. "A CMOS inverter TIA modeling with VHDLAMS," System-on-Chip for Real-Time Applications, 2003, Proceedings. The 3rd IEEE International Workshop on 30 June-2 July 2003 pp. 172-174.

4. T. Taris, J. B. Begueret, and Y. Deval, "A low voltage current reuse LNA in a 130-nm CMOS technology for UWB applications," European Microwave Conference, Oct. 9-12, 2007. pp. 1105-1108.

5. Xiaohua Fan, Heng Zhang, and E. Sanchez- Sinencio, "A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA," Solid-State Circuits, IEEE Journal of Volume 43, Issue 3, March 2008, pp. 588-599.

6. Norlaili Mohd, Noh Zulkifli, and Tun Zainal Azni, "A 1.4-dB Noise Figure CMOS LNA for W-CDMA Application," International RF and Microwave Conference, September 2006, pp. 143-148.

7. S. K. Alam and J. DeGroat, "A 1.5-V 2.4-GHz Differential CMOS Low Noise Amplifier for Bluetooth and Wireless LAN Applications," 2006 IEEE North-East Workshop on Circuits and Systems, June 18-21, 2006, pp. 13-16.

8. Xiaomin Yang, T. Wu, and J. McMacken, "Design of LNA at 2.4 GHz using 0.25-m technology," Silicon Monolithic Integrated Circuits in RF Systems, Topical Meeting, Sept. 12-14, 2001, Technical Digest, pp. 12-17.

9. P. Leroux, J. Janssens, and M. Steyaert, "A 0.8-dB NF ESDProtected 9-mW CMOS LNA operating at 1.23 GHz ," IEEE Journal of Solid-State Circuits, Vol. 37, No. 6, June 2002. pp. 760-765.