Space applications require a phase-lock-loop (PLL) frequency synthesizer that cannot only provide lowphase- noise performance, but operate within a hostile environment. When the PLL must be small in size, low in power, and low in cost, commercial choices are limited. Most are optimized for landbased mobile-communications use.

Space applications usually require high phase-detector comparison frequencies to reduce the phase-noise impact of the PLL divider and phasefrequency detector. Mobile, landbased applications usually require lower phase-detector comparison frequencies to achieve the step sizes needed for different communications channels. This leads to a requirement for high-division-ratio devices in land-mobile applications.

The demand for high division ratios has led to the choice of 10/11 pre-scalers in some commercially derived PLLs1 for space applications. The disadvantage to this approach is that continuous division ratios lower than 90 cannot be achieved. But a PLL developed by Astrium for space applications employs a dual-modulus prescaler that allows continuous division ratios of 12 and higher, allowing higher comparison frequencies for the same output frequency, which can lead to a reduction in overall phase noise. The PLL also incorporates fractional- N dividers2, which allow high comparison frequencies while generating noninteger multiples of the reference clock oscillator. This provides a phasenoise improvement through reduction of the PLL division ratio compared to an integer-N-only solution.

To overcome potential problems due to radiation in space-based applications, a careful selection of semiconductor process and foundry was made, with radiation tests carried out in parallel to the design of the PLL. The key factor in the choice of process was that the phase noise must not be compromised due to the process. A silicon-germanium (SiGe) process was found with radiation-tolerant bipolar transistors while simultaneously leading to a low-noise PLL design.

Cost is also of great importance in the space industry, where the procurement of multiple oscillators can incur large non-recurring-engineering (NRE) costs. If the voltage-controlled oscillators (VCOs) can be integrated into the PLL and if performance is good enough for the customer, large cost savings are possible. With this in mind, the Astrium PLL was designed with on-chip VCOs but with the option to use off-chip parts if desired. One such instance could be where a customer demands the noise performance of a dielectric resonator oscillator (DRO), which is not possible with onchip solutions. Another feature incorporated specifically for space use is a dual serial interface. This allows the connection of a main and redundant interface from the spacecraft control section.

The key design features of the PLL frequency synthesizer include low-noise-floor detectors/ dividers with -219 dBc/Hz typical measured figure of merit (FOM); a dual-modulus prescaler with selectable 4/5 or 10/11 division ratios; and a third-order sigma-delta modulator with 20-b resolution (modulation is disabled when the PLL is operating in integer-N mode). The dual-modulus prescaler can handle input frequencies past 3.5 GHz. The PLL can operate with either an on-chip or off-chip VCO, as selected by the user. The PLL's on-chip VCO tunes from 250 MHz to 3.6 GHz. The PLL chip operates at reference input frequencies to 100 MHz and with comparison frequencies to 100 MHz. It features a dual redundant serial programmable bus for integration and fraction division ratios and provides a choice of parallel programming for integer-N operation

The PLL operates on a +3-VDC supply and draws less than 65 mA current. It's on-chip VCO operates with a +4.85-VDC supply and draws less than 135 mA current. The onchip VCO is disabled when using an external VCO. The PLL chip features an integrated 2 mA/2 charge pump with separate voltage supply (+4.85 VDC) to allow higher control voltages. The PLL has 1.5-V/2 phase frequency detector outputs to bypass the integrated charge pump.

The CMOS digital section of the chip (Fig. 1) provides registers for programming the PLL dividers, the fractional accumulators, and the VCO selection algorithm. The fractional accumulators comprise a third-order delta-sigma circuit.2-4 It incorporates pipelining to allow measured clock frequencies of greater than 50 MHz to be reached. Inputs to the digital section include an 11-b integer-N word (M and A counter values), a 20-b fractional word, a 4-b R-counter word, VCO selection, and a fractional circuitry disable pin. The counter values, fractional word, and VCO selection are programmed serial via a dual-redundant three-wire interface. In integer- N mode only, the counter values may be set with a parallel interface using external pull-down resistors.

The major blocks and connectivity of the analog section of the PLL chip are shown in Fig. 2. The phasefrequency detector (PFD), prescaler, and reference divider section are all implemented in emitter-coupled logic (ECL) to provide high operating speed and good low-noise performance. The design target was for comparison frequencies at the phase detector to at least 100 MHz. Measurements show that the maximum comparison frequency over temperature is greater than 130 MHz. The PFD has inverted outputs available, logic high when in lock, for use with an active loop filter or an optional 2 mA/2 charge-pump output, which is operating off the higher voltage of 4.84 V to increase the available VCO tuning range. The charge pump allows the use of a passive loop filter thereby removing the operational amplifier needed within the active loop filter. However, due to the CP using FET switches, the saving of active loop filter parts needed to be balanced against the FET-generated 1/f noise, which manifests itself as increased close-in phase noise.

The PLL has selectable 4/5 and 10/11 dual-modulus prescalers. The 4/5 prescaler allows integer division rations of between 12 and 528. This allows a user to run at a comparison frequency of 100 MHz while delivering an output frequency of 1.2 GHz. With the 10/11 prescaler alone, this is not possible due to its minimum continuous division ratio of 90. Of course, some may question the need for the additional 10/11 prescaler when having a 4/5 circuit capable of such high-frequency performance. The reason lies in the circuitry beyond the prescalers. These are the M and A counters that must tally the output of the prescaler to give the overall division ratio. The 4/5 prescaler requires these counters run at approximately double the frequency compared to when the 10/11 prescaler is used.

The 4/5 prescaler therefore is guaranteed to operate to 1.6 GHz, limited by M and A counters that follow it. Measurements have shown that the 4/5 prescaler operates well over temperature to 2 GHz. The 10/11 prescaler, which operates at higher frequencies, has a minimum divide ratio of 90, maximum divide ratio of 1296, and accepts input frequencies between 0.2 and greater than 3.5 GHz. Measurements have shown that the 4/5 (10/11) prescaler is capable of operating over temperature at frequencies past 3.5 GHz. The 4-b reference divider has an input frequency range of 1 to more than 100 MHz. In fractional mode, the minimum division ratios are 15 and 93 for the 4/5 and 10/11 prescalers, respectively.

The on-chip VCO block has an output frequency range of 0.25 to 3.5 GHz; the oscillator can be used with either the 4/5 or 10/11 prescaler. The on-chip VCO block can be disabled if an external VCO, DRO, or coaxial resonator oscillator (CRO) is used for extended frequency range of improved phase-noise performance. In support of the oscillator circuitry, a wideband, multiple-octave output buffer provides more than 0 dBm output power in single-ended or differential operation from 250 MHz to 3.5 GHz.

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With multiple VCOs available within the chip, a method must be devised of choosing the required VCO. There are two possibilities available to the user. The VCO choice can be programmed, or the VCO can be automatically chosen by the PLL chip through a recursive search algorithm. The PLL/VCO is designed to allow for automatic VCO selection within a range consisting of 10 contiguous VCO subbands. There are 31 VCO subbands covered by four overlapping automatic tuning ranges. The reason for the four ranges is to ensure adequate PLL phase margin during VCO selection.

The complexity and performance of the integrated PLL/VCO requires the need for bipolar and MOS devices. A 0.5-m silicon-on-insulator (SOI) process was identified at an early stage of the chip development due to its immunity to a single event failure and its excellent tolerance to low-dose radiation levels compared to conventional silicon processes. This allows implementation of high-speed ECL for the phase detector and dividers, low-power MOS for fractional-N and digital circuitry, and bipolar circuitry for the low-phase-noise VCO. The use of bipolar and ECL analog circuitry, although it consumes more power than MOS circuitry, helps lower the 1/f noise and therefore improve the phase noise, particularly at low offset frequencies. The foundry process has been qualified by Astrium to radiation levels of greater than 100 krad using ESA/SCC 22900 radiation and test exposure sequence and flow chart practices along with MIL-STD- 750 electrical test methods.

The power consumption of the PLL depends on the mode of operation. The largest power delta is determined by whether the internal VCO is used. Table 1 shows the power consumption for the chip in three modes of operation. The mode with maximum power consumption is that with internal VCO enabled and the charge pump bypassed. Two voltage rails are required for operation, at +3 and +4.85 VDC. It is recommended that these supply rails are well filtered (or linearly regulated) to ensure the lowest phase-noise performance.

A number of PLL chips were fabricated with the high-performance process on a multiproject wafer (MPW) for performance evaluation. Figure 3 shows the VCO output frequencies and output power, displaying that all VCOs hit their target frequency range and overlap as desired for continuous output frequency capability from 250 MHz to 3.5 GHz. Measurements were made at -40, +25, and +80C for each VCO. The VCO phase noise was measured from 1740 to 3220 MHz and the results are shown in Table 2. The phase noise is competitive with wideband integrated VCOs, which tend to be limited in performance by the qualify factor (Q) of their on-chip inductors.

Figure 5(a) shows a phase-noise plot of the PLL in integer mode at 3300 MHz using the integrated VCOs and the direct PFD outputs (with the charge pump bypassed). A reference and comparison frequency of 100 MHz was used for this measurement. At the 10 kHz offset, according to ref. 1, the PLL achieves a FOM of -221 dBc/Hz. Figure 4(b) shows the phase noise of the PLL in fractional mode at 1922 MHz using a comparison frequency of 20 MHz. Note that the large spurious signal at about 18 kHz offset is generated by the phase-noise test equipment rather than the PLL. The spurious content at 2-, 4-, and 6-MHz offset frequencies are the fractional spurious signals caused by nonlinearities in the PLL's phase detector and/or unwanted on-chip coupling.5 A planned future MPW run will attempt to improve fractional phase noise through a change in the metal mask for the chip.

In summary, the features and performance of a highly flexible integrated PLL/VCO have been presented. The PLL chip is capable of providing any output frequency between 250 MHz and 3.5 GHz without any other active devices required. The design has been optimized for high comparison frequencies and low phase noise typically required in space-based applications for Los. The design has been fabricated on a SiGe BiCMOS on insulator process chosen for its low noise and robust radiation performance. Prototype test results show the PLL chip to be functioning as expected. Further work will include qualification testing to spacelevel requirements, including radiation testing of the device. The PLL will then form the basis for future Astrium Advanced Agile fixed-satellite- services (FSS), generic frequency converters, a product that will be developed as part of the ESA Generic Flexible Payload (GFP) program. The resulting equipment will provide significant cost and schedule savings due to the in-orbit input section frequency planning flexibility. The device will be available as a die or in a ceramic package.

REFERENCES
1. Peregrine Semiconductor, City, CA, model 97632.
2. J. N. Wells, "Frequency Synthesizers," European Patent No. 125790.
3. Andy Howard, "Delta-Sigma Modulator PLLs with Dithered Divide Ratio," Agilent-EEsof, Santa Rosa, CA.
4. David Owen, "Fractional-N Synthesizers," IFR Application Note, Wichita, KS.
5. D. Jiang, P. V. Brennan, and J. Zhang, Intermodulation investigation of Fractional-N Frequency Synthesizer, University College, London, UK.