CMOS LNA Supports Many Receiver Standards

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Xiaodong Cao, Chunhua Wang, Jingru Sun, and Sichun Du

Wireless receivers require front-end low-noise amplifiers (LNAs) to manipulate both ends of the dynamic range. While numerous LNA designs have been developed in support of the wide range of wireless communications standards, this highly linear silicon CMOS designwhich consists of a common-gate stage and a common-source stagecan serve multiple communications standards by merit of its low noise figure, high gain, and wide frequency range of 2.1 to 7.0 GHz. A post-distortion technique employing an additional folded diode is applied to improve the linearity. The LNA boasts 14.6-dB power gain and input third-order intercept point (IIP3) of +21 dBm, with noise figure of less than 3.9 dB and low power consumption of 7.3 mW from a single +0.8-VDC supply.¹

A variety of topologies have been proposed for broadband LNAs, each yielding different results. A shunt-feedback amplifier has difficulty achieving low noise figure and low power operation simultaneously over a broad frequency range.² A distributed amplifier typically has high power consumption.³ An inductively degenerated LNA with LC-ladder network requires a large number of passive components, and thus cannot be made small in size.⁴ A common-gate (CG) amplifier is popular for its capability of providing broadband input matching and high linearity.⁵

High linearity is important in an LNA to suppress interference and maintain good receiver sensitivity. A wideband, multiple-standard receiver must deal with a large number of in-band and out-of-band interfering signals, resulting in severe blocking, cross-modulation, and inter-modulation; these pose a huge challenge to the linearity of the LNA. With CMOS scaling, linearity tends to be degraded at lower supply voltages and due to short-channel and field-field-mobility effects.⁶ In addition, the nonlinear output conductance, mobility degradation, and velocity saturation make efforts to linearize an LNA complicated when working with deep submicrometer CMOS technology.⁷

Several techniques have been proposed to improve the linearity. A peak in IIP3 can be obtained by using the optimal biasing technique, in which the third-order derivative of the DC transfer function characteristic is zero. However, the bias voltage range for peak IIP3 is very narrow, making the linearity boosting process very process-sensitive by using this technique.

Derivative superposition (DS) methods^8-10 are based on multiple gated configurations which add the second- and third-order derivatives from the main and auxiliary transistors to cancel distortion. But wideband DS methods^{11, 12} can seriously degrade impedance matching and noise figure. All of the DS methods mentioned in the literature make it difficult to achieve impedance matching in the different working regions of the transistors. The body biasing method¹³ provides a suitable source-to-bulk voltage as a way to increase linearity, but at a cost of degraded gain and noise figure. Another method,^{14, 15} which subtracts distortion flowing through the common-source (CS) and common-gate (CG) stages of the output transistor, consumes a great deal of power and is limited at higher frequencies. The post-distortion technique⁶ provides a robust increase in linearity, but also hinders input impedance matching.

The LNA reported in ref. 6 exhibited low gain and poor noise figure due to stacking two CG transistors. But employing passive components instead of a source-follower device as the output buffer can provide an improvement in linearity,¹⁶ although the passive components required to do this will occupy a large area of the LNA circuit.

A new approach proposed here was implemented in a broadband LNA design. It adopts a CG structure to provide input matching, in addition to a CS amplifier to enhance gain and output matching. A post-distortion technique employing an additional folded diode was also applied to improve linearity.

First, a review of some fundamental mathematical relationships: The drain current of a CS FET can be expressed in terms of gatesource voltage using the power-series expansion:

where the g⁽ⁿ⁾ parameters represent first-order transconductance and second-order and third-order nonlinearity coefficients. The nonlinear current generated in the CS FET is fully transferred to the next stage. If the drain node of the CS FET has an additional current path which selectively absorbs the third-order intermodulation-distortion current component, only the fundamental current component can be delivered to the next stage. The technique presented here shows that an additional folded diode can work almost like an intermodulation-distortion sinker. Figure 1 offers a conceptual view of the post-distortion technique. Both transistor M_a and M_b operate in the saturation region with the same polarity. Transistor M_b taps voltage V₂ and replicates the nonlinear drain current of main transistor M_a, partially canceling the second-order and third-order distortion terms.⁷ The drain currents of transistors M_a and M_b can be modeled as Eqs. 2 and 3:

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Parameter V₂ can be related to voltage V₁ by Eq. 4:

Since the currents must satisfy the KCL equations, they will yield the output current as shown by Eq. 5:

From basic circuit theory, it is clear that ci has a negative value. To obtain good linearity, the coefficients of the third term in Eq. 5 should be close to zero, by adjusting the gate bias and size of transistors M_a and M_b.

The expression of IIP3 is given by Volterra series analysis:

where:

As can be seen from Eq. 6, IIP3 is mainly affected by the term ε(Δω, 2ω). Equations 6 through 8 imply that linearity can indeed be improved by reducing g_m'', but when g_m'' becomes negligibly small, term ε(Δω, 2ω) becomes dominated by the second term, which is proportional to the square of g_m''. The post-distortion technique employs an additional folded diode to minimize g_m'' and g_m'' simultaneously. Since the bias current and transconductance of transistor M_b are much smaller than the values of the same two parameters for transistor M_a the post-distortion technique does not degrade noise figure or gain.

The LNA is based on the CHRT 0.18-m mixed-signal/RF CMOS semiconductor process, in which all required components can be integrated (rather than using discrete components). Figure 2 shows the complete circuit schematic of the proposed LNA. Because a source-follower configuration will decrease linearity, it was not used in this LNA design.

The CS amplifier with peaking load is adopted not only to enhance the gain under a low voltage, but also provide wideband output matching. Inductor L₁ is inserted to enhance gain bandwidth, resonating with parasitic capacitance at high frequencies.

Inductor L_d2 is chosen to provide peak gain near the center of the pass-band leading to nearly flat overall wideband LNA gain.¹⁷ Besides, R_d1 and R_d2 can improve the gain flatness. Device M₃ is equivalent to a folded diode for absorbing the nonlinear distortion. The bias current and transconductance of transistor M₃ are much smaller than those of M₂. The post-distortion technique is implemented at the second stage, reducing its influence on noise performance and input matching.

For simplicity, most parasitic effects and body effects were ignored. The input impedance can be written as Eq. 9:

The input impedance approximates 1/g_m1 over the frequency band of interest. Due to the effects of the other terms, g_m1 should be set to a value slightly greater than 20 mS. Computer-aided simulations show that the input matching is good when g_m1 approaches 26 mS.

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Figure 3 shows the small-signal equivalent circuit for the output impedance calculation. The output impedance can be written as Eqs. 10-12:

where Z_out1 = the output impedance of the first stage; Z_z(Ω) = a parameter deeply affected by the value of R_d1; Z₃(Ω) = an impedance introduced by auxiliary transistor M₃. Regardless of transistor M₃, at low frequencies Z_g (Ω)g_m2gd2 and Z_out ≈ Z_d ≈ R_d2. If this value is about 50 Ω, the output impedance will be well matched.

With the increase of frequency, the influence of parasitic capacitance becomes enormous. Inductor L_d2 is added to compensate for this influence. Then the wideband output matching is achieved. Taking transistor M₃ into account, the reactive resistance decreases and the capacitive reactance increases, due to M₃ placed in parallel with the load of transistor M₂. Therefore, the values of R_d2 and L_d2 should be adjusted slightly to acquire a new wideband output matching. Here, R_d2 = 43 Ω and L_d2 = 2.39 nH. The body effects and parasitic capacitances were not considered in this analysis. The voltage transfer function of the first stage can be expressed as Eq. 13 (and Eq. 14):

The voltage gain of the CS amplifier is given by Eqs. 15 and 16:

The gain increases with the increase of R_d2, but too large a value of R_d2 degrades the output matching. Parameter L₁ improves gain at high frequencies resonating with parasitic capacitance at the drain node of transistor M₁, while R_d1 improves the gain flatness. The addition of transistor M₃ decreases the gain slightly; however, it is possible to increase g_m2 and decrease g_m3 to compensate for this. The values used for the proposed LNA include R_d1 = 14.5 Ω, L₁ = 7.46 nH. g_m3 = 8.4 mS, and g_m2 = 37 mS.

The noise figure of the first stage is critical to the whole circuit, especially when the CG amplifier has an effective power gain. Capacitance C₂ can bypass the noise contributed by the bias circuit. The noise factor of the first stage can be obtained as shown in Eq. 17.

The noise performance can be improved by increasing g_m1. However, the input matching degrades as g_m1 increases.

The LNA was simulated by means of the Spectre simulation software from Cadence Design Systems and based on the use of the CHRT 0.18-m mixed-signal/RF semiconductor process. By merit of having only one layer of transistors in the amplifier design, the supply voltage drops to 0.8 V. To minimize the bias current, a current mirror was added. The bias voltages for transistors M₁ and M₂ are the same. To lower the power, the bias resistor was selected for a large value and the width of M₄ was made very small. In the proposed LNA, W_m2 = 120 m, W_m3 = 84 m, W_m4 = 1 m, R_bias1 = 1.94 kΩ, R_bias2 = R_bias3 = 10 kΩ, and V_b1 = V_b2= 0.7 V.

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The input reflection coefficient S₁₁ and output reflection coefficient S₂₂ were less than -10.7 dB over the frequency range from 2.1 to 7.0 GHz (Fig. 4 and Fig. 5). The maximum power gain was 14.6 dB at 2.8 GHz (Fig. 6). The noise figure was 3.1 to 3.9 dB across the frequency band of interest (Fig. 7). Isolation was better than 38 dB. The power consumption was 7.3 mW from a 0.8-V supply. The computer-aided simulation indicated that the input third-order intercept point (IIP3) would be about +11 dBm, while the measurements showed IIP3 to be +21 dBm at 4.5 GHz (Fig. 8). Use of the post-distortion technique detailed here can improve IIP3 by about 5 to 13 dB. Figure 9 shows the circuit layout of the LNA, which occupies an area of 0.56 x 0.56 mm. The table compares the performance of the proposed LNA with other reported LNA performance levels, summarizes the performance of the proposed LNA, and compares other reported LNA performance levels, showing its higher linearity, low power consumption, and low voltage operation.

In summary, the post-linearization technique demonstrated in the proposed LNA can improve IIP3 by about 5 to 13 dB. Simulation results showed that the design achieves a +21-dBm IIP3 peak with maximum power gain of 14.6 dB while consuming 7.3 mW power from a 0.8-V supply.

XIAODONG CAO, Lecturer
CHUNHUA WANG, Professor
JINGRU SUN, Lecturer
SICHUN DU, Lecturer
College of Information Science and Engineering
Hunan University
Changsha 410082, People's Republic of China
e-mail: k666xiaodong@126.com

Acknowledgments

The authors would like to thank the Open Fund Project of Key Laboratory in Hunan Universities No.09K011 for financially supporting this research.

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