Wireless engineers are increasingly relying on field-programmable gate arrays (FPGAs) for their advantages in terms of power, functionality, and cost. FPGAs are particularly suitable for emerging wireless applications, which must satisfy stringent power-consumption and cost demands. Such applications include remote radio heads, pico/femto base stations, software-defined radio (SDR), and WiMAX customer premise equipment (CPE). In a white paper, Altera Corp. (San Jose, CA) provides insight into one FPGA product family's ability to address the needs of such wireless applications.

The five-page paper is titled, "Using Cyclone III FPGAs for Emerging Wireless Applications." It begins by looking at the specific needs of emerging wireless applications. For these technologies, original equipment manufacturers (OEMs) need to design products that are scalable, cost effective, flexible, and reusable across multiple evolving standards. This trend invites other requirements including low-cost production, low power consumption, flexibility, and high performance.

Obviously, the note focuses on the Cyclone III family of FPGAs. In terms of functionality, these FPGAs provide up to 3.9 Mb of random-access memory (RAM), 120,000 logic elements, and 288 18 X 18 multipliers. The bulk of the white paper is devoted to a WiMAX pico-base-station example. After providing a block diagram of that base station's functionality, the paper notes that both digital upconverters (DUCs) and digital downconverters (DDCs) use complex filter architectures. Such architectures include finite-impulse-response (FIR) and cascaded-integrator-comb (CIC) filters.

An overview of WiMAX DUC and DDC architectures is provided. The Cyclone III EP3C80 claims to only use a small percentage of resources in order to implement DUC/DDC functions for WiMAX applications. The remaining FPGA can be used for the rest of the application.

The paper's goal is to show how the low power, memory, and multipliers of the Cyclone III FPGAs can be used to implement the WiMAX pico base station's functions in a cost-efficient manner. The paper asserts that the Cyclone III FPGAs' memory blocks and multipliers enable a very cost-optimized implementation of the downlink and uplink OFDMA engines. The FPGAs also can offload DSP functions like Viterbi decoding and interface to the medium-access-controller (MAC) layer. If these FPGAs live up to their claims, they may certainly enable a host of emerging wireless applications.

Altera Corp., 101 Innovation Dr., San Jose, CA 95134; (408) 544-7000, Internet: www.altera.com