Each receiver incorporates a lowpass single-chip receiver, a cryocooler with two temperature stages and appropriate cryopackaging, a temperature controller, interface amplifies, DC bias current source, data-acquisition hardware based on field-programmable-gate-array (FPGA) circuits, and a graphical user interface (GUI). Work on the two test bed systems was supported through an ONR Small Business Innovative Research (SBIR) Phase 3 contract valued at $650,000, with an exercised option of $75,000 to develop an improved analog-to-digital-converter (ADC) chip. As Richard Hitt, chief executive officer (CEO) of Hypres, explains: "Delivering the test bed systems is an outstanding achievement for our entire team and a key milestone for Hypres. The systems can efficiently evaluate the chip design upgrades we develop when configuring our receivers for customers' specific operating parameters." These systems feature an additional temperature-controlled stage to permit integration of a high-temperature superconductor analog filter with Hypres' low-temperature digital electronics.