Once associated with low-speed digital and analog circuits, silicon CMOS is gaining ground in the world of RF/microwave design as device features continue to shrink. The latest CMOS foundry process from Fujitsu Microelectronics America features 65-nm features. To encourage designers to try the process, Fujitsu has announced new process design kits (PDK) that assist customers with both their 65- and 90-nm silicon CMOS processes.
These high-frequency, high-performance silicon CMOS processes are designed for highly integrated analog and RF/microwave designs in consumer, commercial, and industrial applications. The processes have been used in low-power circuits for communications and navigation systems, including chips for WiMAX and Global Positioning System (GPS) receivers. Both low-leakage processes can fabricate transistors with cutoff frequencies in excess of 100 GHz.
Both processes offer double- and triple-well isolation for better noise control. The processes can fabricate core transistors with voltages of 1 to 1.2 V and input/output (I/O) transistors with voltages of 1.8, 2.5, and 3.3 V in the 90-nm process and 1.8 and 3.3 V in the 65-nm process. The high-frequency transistors are supported by metal-insulator-metal (MIM) and metal-oxide-semiconductor (MOS) capacitors (which can be stacked to achieve increased values of capacitance per unit area), silicided and unsilicided poly resistors, and single-ended and differential inductors formed of thick (as thick as 3.3 m) copper wires with integrated ground shields.
In the 90-nm process, the MIM devices feature capacitance of 1.0 and 1.5 fF/m2 while the MOS capacitors exhibit capacitance of 4.4 fF/m2. Silicided polysilicon resistors in the 90-nm process provide 11 Ohms/square resistance while unsilicided polysilicon resistors offer 450 Ohms/square. The 90-nm process supports as many as 10 metal layers for fabrication of circuit elements and transistors, with low-dielectric-constant (k) dielectric layers between each metal layer.
In the 65-nm process, the MIM capacitors deliver capacitance of 1.0 and 1.5 fF/m2 while the MOS capacitors exhibit capacitance of 4.5 fF/m2. Silicided polysilicon resistors provide 20 Ohms/square resistance while unsilicided polysilicon resistors offer 480 Ohms/square. The 65-nm process supports as many as 12 metal layers, also with low-dielectric-constant (k) dielectric between each metal layer.
Engineers interested in applying these CMOS processes to their RF designs are aided by new PDKs containing highly accurate active and passive component models and useful design toolkits. The PDKs, model CS100A-LL for the 90-nm process and model CS200L for the 65-nm process, feature schematic symbols for circuit entry for both active and passive components, MOS varactor (MOSVAR) and SPICE models, layout technology files with parameterized cells, and physical verification command files. These latter files are suitable for performing design-rule-check (DRC) operations and layout-versus-schematic verification as well as parasitic extraction.
The fine-geometry silicon CMOS processes are well suited for low-power system-on-chip (SoC) designs with integrated RF functions for audio/video, wireless, and optical communications applications. Some of the capabilities of such PDKs are detailed in a free white paper offered on the company's web site entitled "Motivatiaon for RF Integration," available at www.fujitsu.com/downloads/MICRO/fma/formpdf/sms_rfcmos.pdf. Fujitsu Microelectronics America, Inc., 1250 East Arques Ave., Mail Stop 333, Sunnyvale, CA 94085-5401; (800) 866-8608, FAX: (408) 737-5999, e-mail: firstname.lastname@example.org, Internet: www.us.fujitsu.com/wafer.