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Mixer linearity is critical to modern communications systems, especially for ultrawideband (UWB) applications, but requires imaginative circuit-design approaches. One novel double-balanced-mixer circuit employs a source degeneration common-source topology where four tail current sources are used as degeneration resistors to improve circuit linearity. To minimize power consumption while operating on a low supply voltage, bulk-injection and forward-body-bias techniques are also employed in this design.


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This double-balanced mixer covers 1.5 to 11.5 GHz with conversion gain of 6.0 to 7.2 dB. It achieves single-sideband (SSB) noise figure of 18.4 to 20.5 dB with an input third-order intercept (IIP3) of about +1.0 to +6.84 dBm , at the same time consuming only 0.46 mW power from a +0.75-VDC supply voltage.

Increasing demand for low-cost, high-performance portable wireless communications has triggered intensive research on CMOS radio-frequency (RF) front-end circuits. It is well-know that with continuous shrinking of the feature sizes in CMOS devices there is a proportional downscaling in the supply voltage; this yields superior active device high-frequency characteristics in term of power consumption, operating speed, and area.1 However, power consumption remains an issue due to limited battery capacity. Consequently, design for low-voltage and low-power radio-frequency integrated circuits (RFICs) have attracted significant attention and numerous advanced circuit techniques have been proposed in the past few years.2-11

Being widely used in wireless transceivers, the mixer is a crucial component that performs frequency conversion. The conventional Gilbert-type mixer provides high-conversion-gain (CG), low-even-order distortion with superior port-to-port isolation, and is thus beneficial for integrated-circuit (IC) applications. However, due to three-level transistor stacking, the supply voltage available to an active mixer is relatively high. Thus, an IC mixer is inevitably constrained by power consumption.

To satisfy the requirements for low-power operation while maintaining acceptable circuit performance, various design strategies and circuit techniques have been proposed in references 12 through 19. A low-voltage architecture using inductor-capacitor (LC) tanks was adopted in ref. 12. Since the LC tanks require no voltage headroom, this approach allows for a relatively large output swing. Unfortunately, the low Q-value of the spiral inductor limits the operation frequency while still occupying a large die size.

A transformer-based architecture was employed for low power in ref. 13, but the transformer imposed a narrow bandwidth limitation. Another modified mixer structure based on a Gilbert-cell topology was reported in ref. 14, where the mixer core design uses PMOS transistor stacking on the NMOS transistor. However, due to the poor performance of PMOS transistors at high frequency, the operating frequency was limited and the supply voltage was still high. This design was deemed unsuitable for low-power and low-voltage applications.

In order to alleviate the limitations imposed on the supply voltage, a folded-switch topology is proposed to reduce the supply voltage without deteriorating other design parameter.15,16 Nevertheless, the DC current between the transconductance and commutating stages is split—not reused—and may consume an increased power consumption even with a reduced supply voltage.

On the other hand, ref. 17 employs a complementary current-reuse topology with a current-bleeding technique to reduce power consumption. This design approach provides the benefit of reusing DC biasing current and reducing the bias current through the IF and switching stages. However, it suffers from relatively low gain and is usually limited to narrowband operation. Passive mixers offer high linearity and low noise figure with little DC power dissipation,18,19 but they have high conversion loss and also limited isolation between the RF and LO ports. Moreover, large LO signals required to drive passive mixers can significantly increase the power consumption of a receiver system.

What follows is a qualitative description of the mixer’s core operation followed by a detailed look at its performance. Figure 1(a) shows the schematic diagram of the mixer core, which consists of a current source stage (M1), a bulk-driven stage (M2), and a PMOS transistor (M3) as an active load. In contrast to a Gilbert-type mixer, the bulk-injection mixer is based on a four-terminal device where the RF and local-oscillation (LO) signals are applied to the gate and bulk of transistor M2, and the intermediate-frequency (IF) signal is pumped from the drain.20 As a result, the proposed mixer can operate at a reduced supply voltage due to its one less stacked stage compared with a Gilbert-type mixer.

Design A Low-Voltage UWB CMOS Mixer, Fig. 1

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Manipulating The Threshold Signal

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In addition, owing to the bulk-injection technique, the parasitic capacitance between the RF and LO stages—which significantly degrades the conversion gain at a high frequency—is eliminated without a matching LC network. Therefore, a widely flat conversion gain can be achieved across the entire bandwidth. Since the LO signal is injected into the bulk of the core transistor M2, the threshold voltage can be manipulated by the LO signal at the body terminal. Typically the threshold voltage of an n-channel MOSFET is given by Eq. 121:

VTH (LO) = VTO + r([2|φF| - VBS(LO)]0.5 - [2|φF|]0.5   (1)

where:

VBS = the source-to-bulk potential difference;

VTO = the threshold voltage for VBS = 0;

r = the body-effect coefficient; and

φF = the Fermi potential with a typical value in the range of 0.3 to 0.4 VDC.22

From Eq. 1, it can be seen that the threshold voltage VTH (LO) of the transistor is a function of the voltage between the bulk and source, VBS, and the device M2 is switched on and off alternately as the LO signal is in the positive or negative phase of the LO. Hence, the mixing function is achieved by the LO signal, which modulates the threshold voltage of transistor M2.

On the other hand, the mixer core is similar to a common-source degeneration structure in a low-noise amplifier (LNA), where transistor M1 not only acts as the tail current source but also as a degeneration resistor to improve the linearity of the mixer. The high output impedance of PMOS transistor M3 is used as an active load to transfer current to voltage for the IF output signal. Moreover, the forward bias voltage VB is employed at the body of M1 to meet the low-voltage-supply design.

Design A Low-Voltage UWB CMOS Mixer, Fig. 2

To suppress the noise influence of the following blocks and reduce the requirement for the gain of LNA, the UWB mixer should exhibit reasonable conversion gain. Based on the schematic diagram of Fig. 1(b), Fig. 2 shows the small-signal equivalent circuit of the bulk-injection mixer core. Assuming that the gate-drain parasitic capacitance, Cgd,  along with body effects are ignored, the small-signal voltage gain, AV, can be solved by means of Eq. 2:

AV =vIF/vRF= -(gm/rop)/[1 + (rop/ r0) + (ron/ r0) + gm ron]   (2)

where:

r0  = the channel resistance; 

ron = the output resistance of transistor M1; and

rop = the output resistance of transistor M3;

gm = the transconductance of NMOS transistor  M2.

Assuming that the local oscillator (LO) signal is an ideal square wave, and the RF signal is mixed with the LO signal and modulated as the desired output frequency, fRF - fLO, where fRF and fLO represent the RF and LO frequencies, the proposed mixer’s conversion gain (CG) can be expressed as Eq. 3:

CG = (-2/π) {gm rop/[1 + (rop/ r0) + (ron/ r0) + gm ron]}   (3)

In practical circuit design, r0 ≈ ron, gmron ≈ 1 + rop/r0, and the expression for conversion gain can be simplified as Eq. 4:

CG ≈ (2/π)(rop/ron)   (4)

From Eq. 4, it can be seen that the conversion gain of the mixer is determined solely by the output resistance of transistors M1 and M3. To achieve high conversion gain with minimum power consumption, the small-gate-width size device M3 is selected to increase the output resistance, and it also should be biased in its active region. This suggests that increases in resistance rop will boost CG to an arbitrarily high value, which is not correct. Since the voltage drop across the active load M3 is proportional to the output resistance, a large value of rop results in a low voltage between the drain and source of bulk-driven stage M2.

The above-assumed condition no longer holds as it is indicated in Eq. 4 when the low output resistance, r0, of transistor M2 is considered, which degrades the conversion gain of the mixer. Another approach for optimum conversion gain is to reduce the output resistance of M1, but at a cost of circuit linearity and power consumption. Therefore, a design tradeoff exists between conversion gain and linearity for the proposed mixer topology.

A mixer must have acceptable linearity to suppress interference and maintain high sensitivity. In a multiple-standard wideband receiver, in-band and out-of-band interference signals can result in severe blocking, cross-modulation, and intermodulation—all challenging to the linearity of the mixer. For low-power applications, a major design challenge is to achieve the required circuit linearity under limited bias conditions. A number of approaches are available for realizing a high-linearity mixer, but limited power schemes discourage additional active circuit implementations.

The post-distortion technique is one such approach available to Gilbert-type mixers.23 The quest to realize high linearity with little DC current consumption has motivated the source degeneration common-source configuration shown in Fig. 1(a). The linearity of this approach can be understood by means of a mathematical analysis, assuming that bulk-injection stage M2 is operated in its active region as it is turned on. Equate current flow through device M2 and rop in Fig. 1(b):

(VDD – vIF)/rop = βn {VG + vRF - [(VDD - vIF)/rop]ron - VTH}2   (5)

βn = (1/2)μnCox(W/L)2   (6)

where:

βn = the transconductance parameter and Cox = the gate oxide capacitance per unit area.

As indicated in ref. 14, the IIP3 can be expressed as:

IIP3 (dBm) = 10log(8c) (7)

c ≈ (1/2βn2)[4βn(VG - vTH)]2 x [{4βn(VG - VTH)ron + 1}0.5 + 1]   (8)

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Conversion Gain/Power Consumption Tradeoff

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Based on Eqs. 7 and 8, it is clear that mixer linearity increases with the output resistance, ron, of transistor M1. However, mixer conversion gain is degraded as depicted by Eq. 4. Hence, a tradeoff between conversion gain and DC power consumption should be reached to achieve relatively high linearity. Figure 3 shows how simulated circuit linearity and conversion gain vary with the value of ron. For this mixer design, the output resistance values of transistors M1 and M2 are 325 and 920 Ω, respectively.

Design A Low-Voltage UWB CMOS Mixer, Fig. 3

Figure 4 shows a complete circuit diagram for the low-power CMOS downconversion mixer. A double-balanced mixer configuration was chosen for enhanced port-to-port isolation. The proposed mixer consists of three parts: a current source stage (M1 through M4), a bulk-driven stage (M5 through M8), and PMOS transistors (M9 and M10) as active loads. In contrast to the cascade structure of a conventional Gilbert-cell mixer, the four bottom NMOS transistors (M1 through M4) are used as degeneration resistors to improve circuit linearity.

Design A Low-Voltage UWB CMOS Mixer, Fig. 4

Meanwhile, a bulk-driven technique is employed for a low supply voltage as presented previously. In addition, a forward body bias technique is introduced to further alleviate the voltage headroom limitation imposed by the use of a low supply voltage. Since a forward body bias voltage (VLO and VB) effectively lowers the threshold voltage, this technique provides the benefit of reducing the operated voltage as well as LO power without compromising device characteristics in term of gain, linearity, and noise figure.

Moreover, current-limiting resistors RB and RLO must be employed at the body terminal to restrict the excessive junction leakage current. Voltages VG and VP represent the gate bias voltage. On-chip capacitors (C1-C2) are applied as DC-blocking capacitors to isolate the input from the DC source. To achieve low-power operation, the three stacked layers of devices are biased in the linearity, subthreshold, and active regions from the bottom up, consuming only about 0.6 mA DC current from a +0.75-VDC supply.

Design A Low-Voltage UWB CMOS Mixer, Fig. 5

The mixer was computer simulated with SpectreRF software from Cadence Design Systems based on chartered 0.18-μm CMOS technology. By employing forward body bias and bulk-injection techniques, the supply voltage falls to +0.75 VDC. The mixer is designed to operate between 1.5 and 11.5 GHz with local oscillator (LO) power of 0 dBm. With an RF input at 5.2 GHz and LO frequency of 5.1 GHz, the simulated downconversion gain versus LO power indicates peak gain of 7.26 dB at LO power levels between 0 and +4 dBm (Fig. 5). The value of 0 dBm was chosen for LO power where conversion gain of 7.176 dB was obtained for the tradeoff between LO power and conversion gain—of particular significance to this low-power design.

Design A Low-Voltage UWB CMOS Mixer, Fig. 6

Figure 6 illustrates conversion gain over a wide RF input frequency range, with conversion gain of 6.0 to 7.2 dB from 1.5 to 11.5 GHz. Figures 7 and 8 show mixer-noise figure performance. Apart from the IF at 100 MHz, the noise figure versus IF is relatively flat, with less than 1-dB variation from 60 to 500 MHz (Fig. 7). Referring to Fig.8, the simulated single-sideband noise figure ranges from 18.4 to 20.5 dB for an RF range from 1.5 to 11.5 GHz at an IF of 100 MHz. The mixer’s relatively large noise figure is due to use of four tail current sources (M1-M4) at the bottom of mixer.

Design A Low-Voltage UWB CMOS Mixer, Fig. 7

Design A Low-Voltage UWB CMOS Mixer, Fig. 8

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Summing Up

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Figures 9 and 10 provide simulation results of the mixer’s input third-order-intercept-point (IIP3) performance. At a RF of 7.5 GHz, two-tone signals with a frequency spacing of 10 MHz and equal power levels of -30 dBm are applied to the downconversion mixer, with a maximum IIP3 of +6.84 dBm (per Fig. 7). With 0-dBm fixed LO power, the measured IIP3 varies from +1.0 to +6.84 dBm when the RF rises from 1.5 to 11.5 GHz (Fig. 10). The power dissipation is 0.46 mW at a +0.75-VDC supply voltage.

Design A Low-Voltage UWB CMOS Mixer, Fig. 9

Design A Low-Voltage UWB CMOS Mixer, Fig. 10

Figure 11 shows a layout for the downconversion mixer, which occupies a chip area of only 0.36 x 0.32 mm2. The table offers a comparison of the mixer’s performance with recently published results. The new mixer structure provides respectable linearity, conversion gain, and acceptable noise performance with low LO power and less power dissipation compared to other recent mixer designs. 

Design A Low-Voltage UWB CMOS Mixer, Fig. 11

Design A Low-Voltage UWB CMOS Mixer, Table

By employing bulk-injection and forward-body-bias techniques, the CMOS downconversion mixer achieves low power consumption at low supply voltage with flat conversion gain from 1.5 to 11.5 GHz. Based on a conventional Gilbert-type approach, the mixer’s new source degeneration common-source topology using four tail current sources as degeneration resistors to improve circuit linearity. Suitable for UWB applications, it exhibits maximum conversion gain of 7.2 dB with SSB noise figure of 18.4 dB and IIP3 of +6.84 dBm while consuming only 0.46 mW power from a +0.75-VDC supply.

Kehao Ma, Master’s Candidate

Chunhua Wang, Professor and Doctoral Supervisor

Xiaorong Guo, Professor and Master’s Supervisor

Wenbin Huang, Student

Hunan University, Changsha, 410082, People’s Republic of China.

Acknowledgments

This work was supported in part by the Open Fund Project of Key Laboratory in Hunan University (No. 12K012). The authors would like to thank the anonymous reviewers for their valuable suggestions, which helped improve the quality of the article.

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References

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