CMOS Technology has emerged as a solid option for low-cost wireless HDMI integrated circuits (ICs) in the 60-GHz band. Recently, two W-Band receivers have been reported by Mehdi Khanpour, Keith W. Tang, and Sorin P. Voinigescu from the University of Toronto, Canada, along with STMicroelectronics' Patrice Garcia. These receivers are implemented in general-purpose 65-nm CMOS technology with a seven-metal "digital" back end.
The 75-to-91-GHz receiver front end comprises a three-stage cascade low-noise amplifier (LNA), double-balanced Gilbert-cell mixer, and a differential DC-to-9-GHz intermediate-frequency (IF) buffer. The noise- and input-impedancematched LNA uses a cascode input stage with shunt-series transformer feedback. In a theoretical and experimental comparison with a conventional inductor-feedback LNA, the transformer-feedback LNA is found to have 0.5 to 1 dB higher gain, a 0.3-to-0.6-dB lower noise figure, and better input return loss.
This receiver boasts a differential downconversion gain of 13 dB, 1-dB compression with 16.2-dBm input power, and a double-sideband noise figure of 8.5 to 10 dB at a 1-GHz IF. From 80 to 92 GHz, transformer feedback makes the return loss better than 20 dB. It is below 10 dB from 70 GHz to beyond 95 GHz. For LO signals in the 80-to-85-GHz range, an LO-to-RF isolation of 60 dB was measured. Measurements of the mixer breakout show a double-sideband noise figure of 8 to 10 dB over the 74-to-91-GHz band. The LNA's 50-Ω noise figure is 6.4 to 8.4 dB in the 75-to-88.5-GHz range.
The S-parameters, noise figure, and optimum source reflection coefficient were simulated after the extraction of the layout RC-parasitics. They confirmed that the input and noise impedance of the transformer-feedback LNA can be matched over a wider bandwidth. This approach also results in a slightly improved noise figure. For a 1.5-V supply, the peak gain and noise figure at 50 Ω are 16 dB and 5 to 6 dB, respectively. The circuit consumes 89 mW (47 mW in the LNA and mixer). See "A Wideband W-Band Receiver Front-End in 65-nm CMOS," IEEE Journal Of Solid-State Circuits, August 2008, p. 1717.