Design An MMIC LNA With GaAs PHEMTs

Low-noise amplifiers (LNAs) are critical for extracting signals from noise in communications receivers. Other techniques are available for controlling noise in a system, including filtering and cryogenic cooling, but high-performance LNAs offer a proven, reliable means of managing communications system noise. What follows is an exploration into the design of a low-power (battery-operated) LNA operating at X-band (8 GHz). The design compares the use of GaAs PHEMT enhancement-mode (E-mode) and depletion-mode (D-mode) transistors in a monolithic-microwave-integrated-circuit (MMIC) structure with the goal of operating on a few milliwatts of DC power.

This low-power operating goal is incompatible with applications dealing with undesired ( blocking) signals. Such applications require stringent filtering and/or LNAs with excellent linearity in the form of high third-order intercept point (IP3). Still, many wireless applications, such as Global Positioning System (GPS) receivers, can make use of a low-power LNA to boost weak signals where there is not the presence of interfering or blocking signals.

The GaAs PHEMTs under consideration for the LNA design are available in two different device profiles: D-mode, with a typical negative gate threshold voltage and E-mode, with a positive gate threshold voltage. The positive threshold voltage simplifies biasing in a battery-powered system. While it is possible to use a single battery to power a D-mode device, this requires consumption of additional DC power into a source resistor to meet the biasing requirements.

In designing the LNA, the first step is to decide which profile provides the best combination of features and performance. The next step is to choose device size. Device size will affect the LNA's bandwidth, DC power consumption, noise figure, and nonlinear performance. For first-order effects, device size should not affect gain and noise figure. However, as the device gets smaller, resistive losses for matching circuits and interconnections will increase relative to the device impedance, effectively increasing the noise figure.

The choice of device size is a critical step in designing a MMIC LNA. The drain bias current affects the noise figure more so than the drain voltage. Additionally, drain bias affects amplifier gain. With insufficient current, gain will be low. Typically, LNAs are biased at 15 to 20 percent of the drain saturation current (IDSS) as a compromise between gain and noise. The IDSS scales with device size, so a larger device will consume more power than a smaller device. One way to reduce DC power consumption is by reducing the device size while maintaining a 15 to 20 percent IDSS bias.

Decreasing the drain voltage will reduce DC power consumption, but the drain voltage must be high enough for the device to operate in its saturation region and enable amplification. In addition to an increased noise figure and reduced gain as a device shrinks, there are other drawbacks in using a too-small device. These include nonlinear effects and susceptibility to interfering signals within the operating bandwidth due to poor IP3 performance. There is also a range of device sizes that is best suited for matching to 50-ohm systems. Devices smaller or larger than this optimal range will tend to reduce bandwidth, perhaps not a concern in narrowband applications but certainly important in more wide-band systems. Thus, the intuitive tendency to make the device as small as possible for reduced power consumption is tempered by other performance issues. Thus, a power consumption goal of a few milliwatts was set for the design.

Once device size, bias current, and bias voltage have been chosen, the next step is to design the LNA's matching circuits. Nonlinear and linear device models or S-parameters are generally available for a typical device, but these are optimized for a specific device size, such as 300 m. Errors increase as the device is scaled upward or downward, although it is often unclear how much the error increases due to this model scaling. Matching circuits are designed using a simulator and the appropriate device model. An iterative design flow is used to develop the LNA design along with the circuit layout, and various checks are performed along the way. Finally, layout design-rule checks (DRCs) are performed before sending the design out for fabrication.

Figure 1 and 2 show the nearly identical layouts of the D-mode and E-mode LNAs, respectively. Because the GaAs fabrication process is equivalent for both devices other than the doping profile, only a slight tweak in the matching circuits was required to optimize the Dmode design versus the E-mode design. Although both designs were optimized for a single bias point, tests were made over a range of voltages and currents to determine performance capabilities and DC power-consumption limits.

While the two LNAs are nearly identical in layout, simulations show better performance for the E-mode PHEMT for the same DC power consumption. Based on computer simulations, the gain, noise figure, and output power at 1-dB compression (P1dB) are better for the Emode design than for the D-mode PHEMT design. Table 1 compares the two LNAs at various DC bias points.

From the simulations, it would appear that gain is typically 2 dB higher for the E-mode LNA than the D-mode LNA for the same DC power consumption. Likewise, the noise figure is typically 0.3 dB better for the E-mode device than for the D-mode device. While the E-mode device appears to provide more output power at 1-dB compression, its DC power consumption increases at higher input power levels making this an unfair comparison. The input and output impedance matching for the two LNAs is nearly identical.

Measured results will show whether the E-mode device performs better than the D-mode device in the low-power LNA design. In comparing the results, note that MMIC process variations can skew the results for the two LNAs unevenly for a single-wafer sample. Simulations are based on statistically average devices. Variations in the PHEMT active layer (i.e., threshold) doping profile is a major cause of what may be evidenced as performance variations between the two devices. Fortunately, all the matching circuits and passive device variations microstrip lines, inductors, capacitors, and resistorsin the two LNA designs will be virtually identical for the comparisons.

The LNA based on the E-mode device boasts more gain and better noise figure at a comparable DC power consumption level than the LNA based on the Dmode device. Measurements were made of the output power at 1-dB compression (P1dB), noise figure (NF), gain (S21), and impedance match (S11, S22) with the results shown in Table 2.

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An HP 8510 vector network analyzer from Agilent Technologies (www.agilent.com) was used with an on-wafer probe station from Cascade Microtech (www.cascademicrotech.com) to test the MMIC die. S-parameters were measured for both designs over a range of voltages from 1 to 3 V. Electromagnetic (EM) simulations using software from Sonnet Software (www.sonnetsoftware.com) of the input and output matching circuits tended to show a slightly higher shift in frequency compared to the original simulations with the Advanced Design System (ADS) from Agilent Technologies. The actual designs shifted much higher in frequency than predicted by either ADS or Sonnet which could be due to errors in modeling the matching circuit, errors in modeling the PHEMT devices, or normal variations due to wafer processing.

The 4 x 12.5 µm (50 µm) PHEMTs were scaled from a nonlinear model for a 6 x 50 µm (300 µm) PHEMT. Errors could result from model scaling. The smaller device would have a higher quality factor (Q), making it more difficult to match and more likely to incur a frequency shift from variations in the modeling or the devices. Measuring some actual 4 x 12.5 µm D-mode and E-mode devices and then re-simulating the LNAs would be a good way to determine how much of the shift was due to PHEMT model variations. Unfortunately, the only individual measurable PHEMTs on the wafer fabrication were standard 6 x 50 µm devices. Figure 3 shows ADS simulations for the D-mode LNA with ADS microstrip models and also with Sonnet EM simulations of the matching circuits versus measured gain. The gain was higher by about 3 dB for the Emode LNA (Fig. 4).

Noise-figure performance was also shifted higher in frequency for the actual devices compared to the predictions. When corrected for cables losses, the measured noise figures were about 1 dB higher than expected. The E-mode device exhibited somewhat better noise figure (and better gain) than the D-mode device. Figure 5 shows the gain and noise figures of the D-mode and E-mode LNAs measured with a noise-figure analyzer.

Output power compression was measured for both devices using a signal generator and a spectrum analyzer. Since the amplifiers shifted slightly higher in frequency compared to simulations, the original predictions at 8.4 GHz were compared to measured data at 8.9 GHz. Figure 6 shows the measured and simulated D-mode LNA output power as a function of input power as well as the gain. Figure 7 shows the output power and gain measurements for the E-mode LNA. Both devices tend to compress at a lower output power than predicted by simulations. This was typical for other designs on the same wafer run which could be due to normal process variations or modeling errors.

Overall, both the D-mode and Emode LNAs demonstrated good performance at extremely low DC power consumption levels. S-parameters were measured at 1.0, 1.5, 2.0, and 3.0 V with 2 mA drain (I_DS) current for both designs with good noise performance and gain. Of course output power will be more limited at lower voltages and DC power consumptions. Output power was measured at 3 V with 2 mA bias for the comparisons. As expected, the E-mode PHEMT device had 2 to 3 dB better gain than the D-mode device with better noise figure by about 0.33 dB on average. The positive gate bias of the Emode device makes it easier to integrate into low-power (battery-operated) devices. In contrast, the D-mode device needs a negative gate-source voltage (VGS) voltage that requires either an additional negative supply or the use of a source resistor combined with a higher drain voltage to convert the design to a single positive supply.

In summary, two similar LNA designs were fabricated as test circuits along with other student MMICs by TriQuint Semiconductor (www.triquint.com) for the Fall 2005 Johns Hopkins University (JHU) MMIC Design Course (EE787). While both designs demonstrated good gain (8 to 12 dB) and good noise figure (3 to 3.5 dB) at very low power consumptions (a few mW), the E-mode device demonstrated significantly better gain and noise figure for a low-power LNA.

ACKNOWLEDGMENTS
The author wishes to thank TriQuint Semiconductor for their wonderful support in fabricating MMICs for the JHU EE787 MMIC Design course since 1989. Two students in the fall 2005 JHU MMIC course, Trang Pham and John Vitamvas, designed a low-power, LNA at Cband (5 to 6 GHz), which inspired these designs for comparing E-mode and D-mode devices in an X-band (8 to 9 GHz) lower-power LNA. Agilent ADS software was used with the TriQuint TQPED foundry library along with Sonnet EM software to model the interconnections for comparison.