Digital RF processors (DRFs) offer the potential of meeting the requirements for a wide range of cellular telephone wireless standards without significant changes in design and hardware. A DRP design is detailed here, with digital receive and transmit sections, although one of the key components within the DRF is the frequency synthesizer, which employs a novel approach to phaselock- loop (PLL) implementation.
Newer cellular telephones are designed for multiple frequency bands. For example, second-generation (2G) cellular handsets typically cover four frequency bands while third-generation (3G) cellular handsets typically operate over three frequency bands. In addition to voice and data services, modern cellular telephones are also required to accommodate numerous other wireless services, including WiFi, Bluetooth, and Global Position System (GPS) functions.
In recent years, design innovations have aimed at integrating a multiband radio into a single chip. The traditional superheterodyne radio architecture has been discarded and replaced by a direct-conversion architecture that can be easily integrated in a standard low-cost CMOS process. Even though the direct conversion architecture is a big step forward, it is still analog in nature.
Many digital alternative approaches have been proposed and well researched. Most of them are not currently practical due to power consumption and size requirements. One interesting digital radio approach pioneered by Texas Instruments came to commercial fruition in late 2002. The approach is called the Digital RF Processor (DRP).1-3
digital The goal of the DRP is to fundamentally change how radio is designed to facilitate large-scale system-on-chip (SoC) integration on nanometer-scale CMOS processes. Because of the heavy digital content, the performance of the chip can be optimized by means of digital techniques. A DRP can be easily scaled and integrated into a baseband processor. The key innovations are: an all-digital frequency synthesizer, an all-digital transmitter, a digitally intensive discrete-time receiver, and real-time complex compensation for RF and digitally assisted RF builtin self test (RF-BIST) functionality. The DRP philosophy is guided by the paradigm that in a submicron CMOS process, time-domain resolution from digital signal edge transition is superior to the voltage resolution of analog signals. For example, the ever-decreasing power supply voltage in deep submicron processes reduces the voltage headroom in analog circuits, thus practical voltage resolution is limited. On the other hand, fast-switching MOS transistors in CMOS processes, with their picosecond rise and fall times, provide excellent time-domain accuracy with fine resolution.
The first DRP test chip was built in 2001, followed by a commercially available single-chip Bluetooth radio in 2002. The first DRP-based GSM chip was available in 2004. A simplified block diagram of a DRP is presented in Fig. 1. DRP-based Bluetooth and GSM SoCs are shown in Figs. 2 and 3, respectively. The design in Fig. 3 includes an extra GSM SoC on the same silicon die to simplify testing.
In a DRP, the two major building blocks are an all-digital transmitter (Tx) and a digitally intensive discrete-time receiver (Rx). One of the most essential parts of the all-digital Tx is an all-digital frequency synthesizer. Figure 4 offers a side-by-side comparison of the new synthesizer architecture with a traditional PLL-based synthesizer. The phase-frequency detector (PFD) and charge pump combination of the traditional design are replaced in the new design with a combination of an accumulator and a time-to-digital converter (TDC). The dreaded dead-zone problem in an analog PFD is eliminated since there is no racing between clock edges. The accumulator-based digital PFD can have a much wider phase-detection range. The charge sharing, mismatch, and finite output clock leakage problems associated with an analog charge pump are completely removed in digital implementation. The TDC is an extra function block needed to improve phase-detection resolution. The bulky analog resistive-capacitive (RC) loop filter of a traditional PLL synthesizer is replaced by a tiny digital loop filter with full programmability for the PLL loop dynamics. A voltage-controlled oscillator (VCO) with varactor tuning element in the traditional PLL synthesizer is replaced by a digitally controlled oscillator (DCO) with a digitally intensive switching bank. The active elements between the VCO and the DCO in the two designs are the same. The key difference is how the varactor is used. In a VCO, the varactor is tuned with a variable continuous analog voltage. The entire capacitance-voltage (C-V) curve is used for tuning. In the DCO, only the flat portions of the C-V curve are used. The effects of frequency pushing and sensitivity to process variations are greatly reduced in the DCO.
Figure 5 shows a functional block diagram of the DRP TX. A frequency command word (FCW) from the processor is sent to the reference phase accumulator to establish the target output frequency. The DCO output goes through an oscillator phase accumulator, which is analogous to the frequency divider in an analog PLL. Both the reference frequency and frequency-divided DCO output are sampled with the high-speed DCO clock to ensure synchronization. The digital phase detector or accumulator is essentially a digital adder. The loop filter completes the whole DRP Tx.
All the building blocks in an analog PLL have their counterparts in the DRP PLL. One part relatively new to RF engineers is the TDC. Figure 6 shows a simplified design for a TDC. The DCO clock is fed into an array of time delay elements, e.g., inverters. The delay per element is in the order of 20 ps in a 130-nm CMOS process. The fractional part of the phase difference between the DCO and the reference frequency will be proportional to the number of triggered flip-flops. The latched flip-flop output forms a bus feeding a thermometer decoder. The thermometer decoder determines if the phase difference is positive or negative based on the trigged output pattern. The phase difference is converted into a binary number. After normalization, output digits are fed as the third input to the digital PFD.
The DRP's Rx is different from a standard direct-conversion receiver.6Figure 7 shows a simplified block diagram for the Bluetooth SoC. The RF input goes through the front-end low-noise amplifier (LNA) and transimpedance amplifier (TA). Downconversion and discrete-time filtering are performed by the multi-tap directsampling mixer (MTDSM). Then the signal goes through an intermediatefrequency (IF) buffer amplifier and is sent to a sigma-delta (S ) analog-todigital converter (ADC), which converts the analog signal to digital bits.
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The MTDSM represents a new feature in the DRP's receiver. Full details on the architecture and design can be found in refs. 4 and 5, with a conceptual representation in Fig. 8. With the MTDSM, analog-to-digital conversion (RF to bits) at RF is not necessary because the sampling frequency is only required to be twice that of the signal bandwidth. In fact, having to incorporate an ADC at RF would increase the design complexity and power consumption while a very tight jitter performance would be required. Inadequate jitter performance would degrade the overall receiver signal-tonoise ratio (SNR). In a DRP, the RF input signal is sampled directly, and then converted into the charge domain. The MTDSM performs direct sampling, followed by multiple steps of down sampling and filtering. Within the MTDSM, there are four steps of discrete-time signal processing (DTSP) within the charge domain. The input is sampled by the history capacitor (CH) and one of the eight rotating capacitors (CR). Capacitor CH is sampled at the full input frequency. Each capacitor CR is additionally rotated at one-eighth the full input frequency. Thus, this approach is equivalent to the accumulation of eight samples of an RF signal on capacitor CR. It can be also viewed as a decimation operation. The decimation offers filtering, essentially an eight-point moving average function or a simple eight-point finite-impulse-response (FIR) filter.
This is the first step of the four DTSP operations within the MTDSM. The second DTSP function gives rise to an infinite-impulse-response (IIR) filter. At each sampling cycle, capacitor CH gets a certain ratio (?, slightly smaller than 1) of the total charge while each CR gets (1 - ?) of the total charge. Since a total of eight CR capacitors take their turns in sampling the input frequency together with history capacitor CH, C retains ? of the total charge of the previous cycle plus the sample from the current RF input. Since the output at any instant depends on the output from the previous cycles and input from the current cycle, it is a DTSP IIR filter. The third step of the DTSP operation involves reading out the content of a bank of four CR capacitors at the same time. It can be considered as a spatial moving average or a FIR filter. The read-out of four CR capacitors and output buffer capacitor, CB, provide the second IIR filter. The two FIR filters provide anti-alias filtering while the IIR filters provide channel filtering prior to the digital baseband filter. Figure 9 shows MTDSM frequency response.
REFERENCES
1. R. B. Staszewski and P. T. Balsara, All-Digital Frequency Synthesizer in Deep Submicron CMOS, New Jersey; John Wiley & Sons, Inc., Sept. 2006.
2. K. Iniewski, Ed., Wireless Technologies: Circuits, Systems and Devices, Chapter 10; R. B. Staszeswski, Digital RF Processor (DRP), CRC Press, ISBN: 978-0-8943-7996-3, Oct. 2007.
3. Edited by K. Iniewski, Ed., Circuits at the Nanoscale: Communications, Imaging and Sensing, Chapter: K. Waheed and R. B. Staszewski, Mitigation of CMOS device variability in Digital RF Processor, CRC Press, ISBN: 978-1-4200-7062-0, Sept. 2008.
4. R. B. Staszewski et al., "Charge-domain signal processing of direct RF sampling mixer with discrete-time filters in Bluetooth and GSM receivers," EURASIP Journal on Wireless Communications and Networking, Vol. 2006.
5. R. B. Staszewski et al., "Alldigital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS," IEEE JSSC, December 2004.
6. Louis Fan Fei, "Standard Cell Based Modular RFIC Design Considerations," Microwave Journal, April, 2008.