There is still much room for improvement in linearity and low-frequency stability when developing high-power silicon LDMOS devices, as modifications to a standard device can show.
Power lateral diffused metal-oxide-semiconductor (LDMOS) transistors, popularly used in linear high-power amplifiers (HPAs) for cellular base stations, are not without their linearity and stability problems. In addition to long-term threshold drift, stability problems have recently surfaced which include short-term "memory" problems requiring complex and expensive corrective circuitry. To examine these problems more closely, the "hot-electron" problem inherent in all current production LDMOS devices will be investigated and correlated with both short- and long-term device characteristics related to hot electrons. This article will also explore a novel design approach that not only eliminates the hot-electron problem completely, but may also allow a dramatic improvement in device linearity.
The LDMOS threshold drift problem has been discussed for many years. Most of the focus has been on hot electron injection into the gate oxide, causing a drift in the threshold voltage of the LDMOS device,1-3 changing the idling current, (Idq), with time. This, in turn, affects the gain, output power, and linearity of the circuit. Recent reports have documented short-term "memory" effects that have proven annoying to RF circuit designers.4,5 It appears that these short-term effects can be controlled (to some extent) by including a capacitor network in the bias circuit, reducing the nonlinear characteristics of the amplifier. As will be shown, these short-term effects are most likely the result of current/voltage distortion in the transfer characteristics of the device, brought about by driving the LDMOS transistor into secondary breakdown.6
The secondary breakdown effect is encountered because of the parasitic bipolar transistor inherent in an LDMOS transistor. The effect is exacerbated by the shallow drain diffusion incorporated into all current commercial devices. The shallow drain is necessary to reduce the Miller capacitance (from gate to drain), which is critical for high-frequency operation. This, in turn, produces very high electric fields in the drain, a result of dropping a high voltage (~28 V) across an extremely narrow distance (~0.4 µm).
Secondary breakdown has long been known as a frequency-dependant effect. This is due to the accumulation of hot electrons into a destructive current of sufficient magnitude to harm the device (over time). For high-frequency silicon power transistors, the current/voltage swing across the drain is sufficiently swift that destruction usually can't occur. However, if the high-frequency device is then used in a low-frequency application, or is modulated with lower-frequency signals at high peak powers, a destructive current has more time to accumulate. Under such conditions, a device could then be damaged and nonlinear power distortion will likely be apparent in the device's output waveforms.
This onset of secondary breakdown is most likely the effect recently described as a "memory" effect.4,5 In such a case, the electric field in the device is sufficiently high, and the current through the drain is high enough, to trigger secondary breakdown. This results in distorted output waveforms with observable harmonic nonlinearities, although is usually not serious enough to damage the LDMOS device. The device's capacitor network tends to reduce this distortion by attempting to hold the drain current constant. An interesting experiment would be to study the distortion of the LDMOS device at much-lower frequencies, since it is expected that intermodulation distortion (IMD) would increase dramatically under secondary breakdown conditions. For this reason, most production microwave LDMOS devices cannot run safely at frequencies below 100 MHz.
Secondary breakdown is also the reason that all high-frequency power bipolar transistors require emitter ballast resistors—to reduce this effect. Power transistors that operate above several hundred megahertz require these ballast resistors to limit these destructive effects and provide reliable operation. Lower-frequency power transistors (in the kilohertz range) operate reliably without them, simply because they have much wider base widths and much thicker collector regions. The wider bases and thicker collectors (analogous to the drains of a power FET) dramatically lower the electric field in the device, reducing the tendency to be driven into secondary breakdown. Base widths (or channels) of low-frequency devices tend to be many microns in length, compared to fractions of a micron for high-frequency devices. Collectors (drains) in lower-frequency devices are similarly thicker, providing a measure of localized ballast.
A sketch of a typical LDMOS device (Fig. 1) indicates the position and thickness of the drain. The figure also shows a self-aligned shadow-isolated device with a much-thicker epi drain, believed to be free from ALL hot electron effects. Note that the 2.5-µm-thick N-drain epitaxial region and 8-µm-thick P-epitaxial layer reduces the field in a thick-drain LDMOS device by roughly an order of 5 to 10 over a conventional polygate LDMOS device utilizing a shallow diffused drain. The thicker epitaxial drain also allows higher saturated drain current, increasing device linearity at high current.
The electric fields in the two LDMOS devices can be approximated by Fig. 2. The thick-drain device allows for about a 5-to-10-fold reduction in the electric field (due to the much-wider depletion region). This should allow for both an elimination of the threshold shift problem and a dramatic improvement in secondary breakdown characteristics, supporting operation at significantly lower frequencies. This, in turn, should eliminate the long-term threshold drift and short-term memory effects.
The effects of the parasitic bipolar transistor and the high field resulting from the thin drain region can be seen in the transfer characteristics and the breakdown voltage of various LDMOS devices. Figure 3 shows how the breakdown voltage and the device transfer characteristics can be altered by decreasing the resistance across the parasitic bipolar transistor and increasing the drain thickness.
One of the most dramatic improvements made possible by the thick-drain LDMOS configuration is the improvement in the current-carrying capability of the device. This allows not only a reduction in the on-resistance7 of the device, but also a substantial improvement in the high-current capability of the device, increasing linearity at high power levels. Figure 4 compares the current flow in a thick-drain LDMOS device to that of a LDMOS device with shallow drain with conventional (non-self-aligned) polygate. Note that current is restricted by the 0.4-µm shallow diffused drain. This not only effects the maximum current capability of the device, but also the point at which nonlinear effects begin to influence the device at higher currents.
An early version of a shadow-isolated LDMOS device allowed for a 50-W pulsed device with 7-dB gain across the 960-to-1215-MHz band. The design, which was fabricated with the same processes used for vertical DMOS device production at the time, traded gain for bandwidth. The early LDMOS devices suffered from very high Miller capacitance since they had no thick oxide bump over the drain (Fig. 5).
Once the hot electron problem had been resolved, a modified device structure is proposed which would dramatically improve the inherent linearity of the shadow LDMOS structure of Fig. 1. The new approach was discovered by accident some years ago. While working on a contract to improve the linearity of a low-frequency (2-to-30-MHz) device for a military customer, a puzzling observation was made. In this case, the structure of a 1-GHz device was modified to lower its Miller capacitance and improve its high-frequency performance. The modified device incorporated a manually aligned "thick oxide bump" over the drain portion of the gate oxide of a vertical DMOS device. Since the devices were shadow isolated, the parasitic resistor across the emitter-base junction (of the intrinsic bipolar) was already minimized, so it was felt that the resulting DMOS device should operate reliably at much-lower frequencies, even though the lower Miller capacitance wasn't beneficial at the much-lower frequencies. The work was important because the military contract required thousands of reliable high-power devices.
With this modified device, it was possible to parallel eight 50-W 1-GHz chips into a push-pull beryllium-oxide (BeO) package to achieve 300 W output power even at lower frequencies, essentially due to the "accidental" construction of the manually aligned oxide "bumps," intended for better high-frequency response. One wafer from the production lot (which was chosen because the lot yielded thousands of chips for the linearity experiment) exhibited dramatic improvement in device linearity. An improvement of approximately 6 to 8 dB in IMD performance was observed, which was puzzling for a long time. The sketch in Fig. 5 demonstrates what most likely happened and why a similar self-aligned device with dramatically improved intermodulation characteristics now seems feasible.
The "bumps" were created by applying the gate mask to the wafers with a thick oxide and over-etching (under-cutting the images) sufficiently to create a thick bump. The case B wafer (which was likely the test wafer) was minimally over-etched, resulting in a wide bump. The case A wafers were grossly over-etched, resulting in a much-narrower bump. A thin gate oxide was then grown (~1000 Angstroms) and the same gate mask reapplied (using a very skilled operator). The "bumps" had to be very carefully manually aligned since any misalignment would cause serious device problems. It was felt that this process would not be production worthy until a method of self-alignment was perfected. For the purpose of the experiment, however, that problem was eliminated by grossly over-etching all but one wafer, leading to the situation of Fig. 5.
For that wafer lot and one exceptional wafer, it has been surmised (and this hypothesis must still be proven experimentally or modeled via computer) that since the P-diffusion was aligned to the gate oxide, the P-diffusion region extended farther under the bump in the case B. Since the tail of the P-diffusion was covered by a tapered thick oxide, in case B, its turn-on characteristics were altered in a manner that proved very beneficial for the linearity characteristics of the device. A symmetrically tapered oxide over the low P-concentration region, now places thicker oxide over the low threshold region of the channel, actually increasing its subthreshold (low-current) turn-on voltage. Two devices resulted: narrow bump (case A) and wide bump (case B) devices of Fig. 6.
Note that the saturation region of the MOSFET is unaffected by the thick oxide. However, the low-current region should have much more linear characteristics, over the lower-current ranges. If IMD is considered a power-related phenomena, then the more linear (turn on) characteristics of the case B device will keep significantly less distorted power from being supplied to the amplifier, at lower power levels, increasing circuit linearity.
Since a device's linearity characteristics degrade at higher current,5 a device can be kept in relatively linear conditions by reducing operating power levels (staying out of the curved, nonlinear, upper portion of the curves of Fig. 6). At lower current levels, however, the device can only be kept out of the nonlinear region by operating under Class A rather than Class AB conditions. Note that our tests were under Class AB conditions, since the devices operated at the 300-W level.
These device improvements demonstrate two significant effects important to linear amplifier manufacturers:
The self-aligned tapered oxide portion of the shadow-isolated LDMOS device can easily be optimized for significantly improved device linearity. This effect would be nearly impossible to optimize on a more-conventional polygate device. The shadow-isolated device employs self-alignment to accurately locate the bump and shape it over the channel diffusion. This should allow its location and shape to be reproduced within a few hundred angstroms from lot to lot, allowing extremely high-yield LDMOS devices with dramatic improvements in device linearity.