CAPACITY AND BANDWIDTH EFFICIENCY IN CURRENT AND EMERGING wireless communications formats such as Long Term Evolution (LTE) systems are driving the design of smaller base stations with multiple-carrier capabilities. The complex architectures in these systems, such as the use of multiple-input, multipleoutput (MIMO) antenna schemes, require even greater levels of integration in both base stations and handsets. Since many of these systems require variable gain control, which is typically implemented in the form of discrete digital step attenuators (DSAs), reducing the size and cost of that particular function can greatly impact the design of a fourth-generation (4G) wireless communications system. Fortunately, the development of highly integrated digital variable-gain amplifiers (DVGAs) by Analog Devices, such as the models ADL5201 and ADL5202, single- and dual-channel integrated circuits (ICs), respectively, provide 31.5-dB gain control range for intermediate-frequency (IF) applications through 1 GHz.
Figure 1 shows a functional block diagram of a 2 x 2 MIMO wireless transceiver. Variable gain is used at multiple points in the signal chain and serves multiple purposes. The most obvious use is in the receive path where gain is adjusted to optimize the signal level as power levels received by the antenna vary. While low signal levels at the antenna generally demand high gain, variable gain is also used to reduce signal levels when a large unwanted blocking signal is present. In this mode of operation, gain must change quickly and some form of automatic gain control (AGC) is generally employed. DSAs are also used to adjust the static gain of a receiver. Here the gain is set to a particular level to compensate for gain variations of other elements in the signal chain. These variations may be due to part-to-part component variations, gain drift versus temperature, or gain variations versus frequency. With sufficient gain-control range, a single device can be used for both static and dynamic gain control.
In transmitters, there is a similar need for variable gain. As in the receiver, the gain of the transmitter needs to be adjusted so that the gain uncertainty of other components in the signal chain can be calibrated away. In addition to this, dynamic gain control is required to vary the power levels at the antenna to compensate for changing environmental conditions along with the varying distance to the receiver (in mobile application). When transmitter gain is being adjusted dynamically, small step sizes are favored to minimize the spectral splatter that is associated with the gain change.
In a 2 x 2 MIMO radio, as many as six variable gain elements may be employed. With the need for smaller footprint and higher density radio transceivers, in 2007 Analog Devices introduced the first silicon-germanium (SiGe) dualchannel integrated IF digital variable-gain-control solution for cellular base stations, the model AD8376. The DVGA IF amplifier featured differential inputs and outputs and could replace four discrete devices. It offered a 3-dB bandwidth of 700 MHz with gain range of -4 to 20 dB. Providing 1-dB step size with accuracy of 0.2 dB, this earlier VGA featured a noise figure of 8.7 dB at the maximum gain setting. The models ADL5201 and ADL5202 take the DVGA concept one step further by providing a smaller gain step size and additional flexibility in the gain-control interface.
In recent years, the use of differential IF components have steadily increased. This trend is most prevalent in receivers, particularly between the mixer and the analog-to-digital converter (ADC), since most ADCs have differential inputs. These inputs have traditionally been driven by balanced-unbalanced transformers (baluns), which in turn are driven by single-ended RF amplifiers. With single and double-balanced mixers being naturally differential and in some cases providing integrated differential IF amplifiers, there is a strong argument for an all-differential IF strip that is free of baluns and their performance variations stemming from manufacturing tolerances. There are also strong technical arguments in favor of an all-differential IF receiver signal chain as differential components provide excellent immunity to unwanted common-mode signals and natural cancellation of even-order harmonics.
The single-channel model ADL5201 and dual-channel model ADL5202 DVGAs are optimized for use in IF sampling receivers. The ADL5201 is suitable for single-channel receivers while the dual-channel ADL5202 is suitable for use in main and diversity or MIMO receivers. Figure 2 shows a block diagram of the dual-channel ADL5202, while Fig. 3 displays gain versus frequency for each of the ADL5201's 64 gain states. Precise gain control is possible through 1 GHz. For the most common IFs used between 70 and 300 MHz, the ADL5201 and ADL5202 exhibit minimum amplitude variations over frequency, allowing designers to choose an optimum IF for their design while providing precise compensation of gain variations. Both devices feature novel and flexible gain control interfaces. With a gain range of 31.5 dB (-11.5 to 20 dB), these devices can be used to expand the dynamic range of high-performance IF sampling receivers. In addition, a gain-control step size of 0.5 dB ensures that the full input range of the ADC can be fully utilized.
The ADL5201 and ADL5202 DVGAs have three gain-control modes. In addition to parallel and serial interface options, a novel up/down mode is also available. When operated in parallel mode, the 6-b gain code can either be latched into a register or the register can be made transparent resulting in the gain following the code on the six gain-control pins. In serial mode, the gain is set by clocking serial data into the devices' serial to parallel interface (SPI), which also has a read-back mode. In the serial mode, there is an additional fast attack mode where rather than setting the gain to a specific level, the gain can be changed by 2-, 4-, 8- or 16-dB step increments or decrements. The gain can also be changed using an up/ down interface. This allows the gain to be incremented up or down in steps of 0.5, 1, 2, or 4 dB.
The gain-control interfaces of the ADL5201 and ADL5202 DVGAs are designed to allow simple interfacing to ADCs from Analog Devices, such as the AD9643 that features over-range detection. When the ADC is connected to an ADL5201 and ADL5202 DVGA's up/down interface, over-range detection at the ADC's output port starts decreasing the gain until the ADC is no longer in an over-driven condition. A parallel digital interface is commonly used with high-speed AGC circuits, and the up/down and fast-attack modes in the ADL5201 and ADL5202 DVGAs reduce the number of control lines for simpler printed-circuit-board (PCB) layouts and reduced PCB real estate.
The ADL5201 and ADL5201 provide outstanding linearity, with an output third-order intercept point (OIP3) of better than +50 dBm at the high end of the gain range at IFs to 150 MHz (Fig. 4). Another key feature of the ADL5201 and ADL5202 DVGAs is the low-power mode, which reduces the supply current by 25 percent compared to the standard operating mode. Operating in the low-power mode results in a moderate drop in linearity, but the mode can be switched on and off based on dynamic conditions in the receiver. For example, under normal receive conditions, the low-power mode could be used with the higher linearity mode only being turned on when large in-band blockers are present.
As companion products to the ADL5201 and ADL5201 IF DVGAs, a pair of GaAs-based variable-gain amplifiers (VGAs) has been developed for RF applications. The RF VGAs integrate a DSA with 0.5-dB resolution with a single amplifier stage in the model ADL5240 and with two amplifier stages, one on each side of the DSA, in the model ADL5243. Both single-ended 50-Ω RF DVGAs can be used in both receiver and transmitter applications from 100 MHz to 4 GHz.
The ADL5240 is a high-performance DVGA that integrates a DSA with a broadband, fixed-gain amplifier. The amplifier is internally matched and has a broadband gain of approximately 19.5 dB. The 6-b DSA has a 31.5-dB gaincontrol range, 0.5-dB step size, and 0.25 dB step accuracy over the entire frequency range. DSA attenuation can be controlled by using either a parallel or serial interface mode. The ADL5240 operates from a single supply voltage of 4.75 to 5.25 V with low quiescent current of 90 mA.
The DSA and amplifier in the ADL5240 can be wired for the attenuator to drive the amplifier, for transmitter applications, or for the amplifier to drive the attenuator, for receiver applications. The ADL5240's +38-dBm OIP3 and noise figure of about 3 dB (at 2 GHz) combine to make the device attractive for both receiver and transmitter signal paths. The digitally controlled VGA achieves +19.1 dBm output power at 1-dB compression when evaluated at 2 GHz. It is housed in a thermally enhanced 5 x 5 mm 32-lead LFCSP package.
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The ADL5243 provides a higher level of integration compared to the ADL5240. Along with a broadband amplifier and a 31.5-dB DSA, the ADL5243 includes a second amplifier. This allows the device to be configured in an amplifier-DSA-amplifier component lineup (Fig. 5). This configuration is designed for use after the final RF upconversion stage within the base station transmitter. The final stage amplifier is designed to deliver a highly linear output power capable of driving directly into a base station power amplifier. When the three components are connected in the abovementioned configuration, they provide a cascaded gain of 29 dB when the DSA is set to minimum attenuation. The ADL5243's final stage amplifier is designed to deliver highly linear output characteristics, with OIP3 of +41 dBm for two +10-dBm signals (Fig. 6); this final-stage amplifier is capable of directly driving a base station's power amplifier. Like the ADL5240, the DSA attenuation in the ADL5243 can be controlled either by a parallel or serial interface mode and support 0.5-dB steps like the IF DVGAs.
The ADL5243 operates from 100 MHz to 4 GHz with a 31.5-dB gain control range that is adjustable in 0.5- dB steps with 0.25-dB step accuracy. Amplifier 1 delivers 20 dB gain at 900 MHz with +20 dBm output power at 1-dB compression and an output thirdorder intercept point of +38.2 dBm at 900 MHz. The noise figure is 2.9 dB at 900 MHz. Amplifier 2 provides 16.9 dB gain at 880 MHz with +25.4 dBm output power at 1-dB compression. It has an output third-order intercept point of +25.4 dBm at 880 MHz. Like the ADL5240, it is designed for a single supply of 4.75 to 5.25 V with low quiescent current of 195 mA. It is also supplied in a 5 x 5 mm 32-lead LFCSP package.
For a 2 x 2 MIMO LTE application, the RF/IF DVGAs provide a 64-percent decrease in component count with a further significant decrease in PCB area due to minimal requirements for external impedance matching components. The high linearity, low noise, and low-power consumption provide significant performance advantages compared to discrete solutions. An added benefit of the high level of integration is the reduction in number of voltage supply pins and supply current. For example, the ADL5202 reduces supply pins over discrete implementations and reduces device current by more than 50 percent over discrete solutions. When coupled with the integration advantages and reduced system and cost complexity, the RF/IF VGA solutions enable small footprint designs for next-generation LTE radios. Analog Devices, Inc., 3 Technology Way, Norwood, MA 02062; (781) 329-4700, Internet: www.analog.com.