Integration has been critical to RF electronics in mobile handsets, although elusive to achieve in infrastructure equipment. The classic tradeoff in achieving integration has been the choice between using discrete components, with their superior performance, or integrated circuits (ICs), with their small size. Recently, Analog Devices has developed a series of highly integrated phase-lock-loop (PLL) circuits that also combine in-phase/quadrature (I/Q) modulators, local oscillators (LOs), and output baluns within a 6 x 6 mm package. The RFICs leverage SiGe BiCMOS technology to achieve small size without sacrificing electrical performance. The eight devices in the ADRF660X and ADRF670X families provide RF outputs from 300 to 3600 MHz in support of a wide range of wireless communications standards.

The ADRF670x devices combine a quadrature modulator, a fractional-N PLL, and an integrated voltage-controlled oscillator (VCO). The ADRF660x devices integrate a fractional-N PLL and VCO with a downconverting mixer optimized for the digital-predistortion (DPD) path. The use of SiGe technology helps achieve wide dynamic range in both the quadrature modulator and mixer while also integrating a VCO with outstanding phase noise that is competitively priced and significantly smaller than external VCO/PLL solutions.

In the ADRF670X series (Fig. 1), model ADRF6701 has an LO range of 750 to 1160 MHz with a 1-dB RF output range of 550 to 2200 MHz and 3-dB RF output range of 400 to 1300 MHz. Model ADRF6702 has an internal LO range of 1550 to 2150 MHz with 1-dB RF output range of 1550 to 2200 MHz and 3-dB RF output range of 1200 to 2400 MHz. Model ADRF6703 features an internal LO range of 2100 to 2600 MHz with 1-dB RF output range of 1900 to 2400 MHz and 3 dB range from 1600 to 2600 MHz. Model ADRF6704 operates with LO signals from 2500 to 2900 MHz with a 1-dB RF output range from 2400 to 2800 MHz and 3 dB range from 2200 to 3000 MHz.

In the ADRF660X series (Fig. 2), model ADRF6601 works with LO signals from 750 to 1160 MHz and provides RF outputs from 450 to 1600 MHz flat within 1 dB and from 300 to 2500 MHz flat within 3 dB. Model ADRF6602 works with LO signals from 1550 to 2150 MHz and provides RF outputs from 1350 to 2750 MHz flat within 1 dB and from 1000 to 3100 MHz flat within 3 dB. Model ADRF6603 has an LO range of 2100 to 2600 MHz, 1-dB RF output range of 1450 to 2850 MHz and 3-dB RF range of 1100 to 3200 MHz. Model ADRF6604 has an LO range of 2500 to 2900 MHz, 1-dB RF output range of 1600 to 3200 MHz and 3-dB RF range of 1200 to 3600 MHz.

Many design aspects were considered in the development of the ADRF660X and ADRF670X RFIC families. For example, LO synthesis and distribution is critical for the upconversion and downconversion stages of a transmitter printed circuit board (PCB). The LO signal paths must be designed with great care, since unwanted coupling can degrade transmitter performance. The lengths of the traces from LO to final termination should be as short as possible. One solution is to feed a common reference to separate phase-lockloop (PLL) synthesizers near each LO, although this adds PCB real estate.

In most wireless communications transmitter designs (Fig. 3), the power amplifier (PA) dominates the distortion budget. To achieve high linearity, these amplifiers often draw large amounts of supply current. Highlinearity amplifiers are a significant portion of the hardware cost in a transmitter, and are expensive to run due to their high current demand. The use of DPD involves a transmit observation receiver (TOR) to measure the output spectrum of the transmitter. The TOR receives its signal from a directional coupler at the output of the PA. Initially, the base station is run in a mode that allows the TOR to collect information on the distortion characteristics of the power amplifier. In the digital processing core of the base station, this information is used to predistort the transmitted signal, thus compensating for the distortion of the PA and allowing the use of a lessexpensive amplifier while still meeting the distortion budget. The ADRF670x and ADRF660x RFICs families solve many of the integration problems for both transmit and DPD signal paths.

To form high-quality-factor (high-Q) on-chip inductors as part of the inductive- capacitive (LC) tank circuit for their VCOs, the ADRF670X and ADRF660X families VCO utilize thick metal layers. The VCO capacitor is formed using metal-oxide-semiconductor (MOS) switchable metal-insulator-metal (MIM) capacitors that allow the VCOs to switch frequencies over wide frequency ranges with low phase noise (Fig. 4).

The VCO is locked to an external reference using a fractional-N PLL (Fig. 5). The fractional-N PLL allows for very low levels of in-band phase noise resulting in excellent integrated transmit noise and excellent transmit error-vectormagnitude (EVM) performance. The PLL provides the option of selecting the input reference frequency due to a flexible input multiplier/divider circuit. The PLL also includes a wide-range, programmable-modulus third-order sigma-delta modulator as well as a programmable charge pump circuit. As an example of the performance possible with this approach, the close-in phase noise for the ADRF6702's LO is better than -108 dBc/Hz measured 100 kHz offset from a 2-GHz carrier (Fig. 6).

The fractional-N PLL design of the ADRF670x and ADRF660X families is ideally suited for 3G and 4G applications requiring low phase noise. Traditionally, PLLs use fixed-integer multiplication factors. To provide small frequency step sizes, the integer multiplication factor must be very large but this exacerbates the problem of noise on the PLL output. A significant amount of LO phase noise originates in the reference path and is amplified by the PLL frequency multiplication factor. However, a fractional-N PLL allows small frequency steps while using a relatively low frequency multiplication factor, therefore reducing phase noise associated with integer-N PLLs.

With an integer-N PLL at a steady-state condition for a given reference input frequency, the VCO frequency can only be one of a discrete number of values, that number being equal to the number of possible values of the divider between the VCO output and the phase-frequency-detector (PFD) input. Since the divider values are all integers, the PLL output frequency can only be an integer multiple of the reference input frequency. In a fractional-N PLL, the dividers switch between two different integer divider ratios, thus providing an overall ratio that is the average of the two. The average ratio can easily be set to a fractional number. The lowpass operation of the loop filter eliminates the transient that results from switching between the two ratios, and the voltage present at the VCO input represents a frequency that is a fractional multiplication of the reference input frequency.

As an example of "fractional-N" operation, consider a divider network broken into five cycles. For four of those cycles, the divider ratio is set to eight, and for the fifth divider cycle, the ratio is set to 10. So, for 42 VCO cycles , the divider output generates five cycles. The average divider ratio is therefore 5/42, and the frequency multiplication is the inverse of this, or 42/5. So, the frequency multiplication is the sum of an integer value (8) and a fractional value (2/5). These numbers are directly programmable in the ADRF670X and ADRF660X series, represented as an integer, fractional, and a modulus value within the PLL serial peripheral interface (SPI) registers. A wide range of values are possible for integer, fraction, and modulus controls. The integer can be programmed from 21 to 123 (decimal), the modulus from 1 to 2047, and the fractional value from 0 to the modulus value minus 1.

Fractional-N PLLs often suffer from spurious levels close to the fundamental frequency. To overcome this limitation, the ADRF670x and ADRF660X families feature a sigma-delta modulator to distribute the fractional value around the mean. This minimizes spurious with no other significant tradeoff in performance. The SPI allows a user to adjust functions such as charge-pump offset current and polarity to optimize PLL performance.

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The quadrature modulator core within the ADRF670x family represents an improvement over modulators already developed by the company. In these new modulators, baseband inputs are first converted to currents and then mixed to RF signals using high-performance NPN transistors. The mixer output currents are transformed to a single-ended RF output using an integrated RF balanced- unbalanced (balun) transformer. The high-performance active mixer cores, coupled with the low-loss balun, results in exceptional output third-order intercept-point (OIP3) and 1-dB outputpower performance, with a very low output noise floor for exceptional dynamic range. The use of a passive transformer balun rather than an active output stage leads to an improvement in OIP3 with no sacrifice in noise floor. Over the specified frequency range, the four RFICs in the ADRF670x family typically provide 1-dB-compressed RF output power of +15 dBm and OIP3 of +30 dBm. The RF noise floor is -157 dBm/Hz. Typical image rejection is 40 dB without I and Q gain compensation.

The I/Q modulator includes a LO quadrature divider that takes the VCO output (at two times the LO frequency) and generates quadrature LO signals for the two mixers. The divide-by-two LO function in the modulator eliminates the need for an internal passive quadrature filter network, improving modulator image-rejection performance over wide frequency bands. High-gain balanced amplifiers in the LO chain reduce the effects of LO amplitude variations.

A critical design challenge in creating the ADRF670X family of RFICs was to minimize coupling between the integrated passive magnetic components and external interference. Coupling between the VCO inductor and the RF transformer balun can lead to degraded transmit adjacent-channel power ratio (ACPR) performance that impacts overall transmit performance.

To demonstrate, Fig. 7 shows the relationship between this coupling and output ACPR for a WCDMA transmitter. As the coupling coefficient increases between the VCO and the transmitter balun transformer, the ACPR for the first adjacent channel degrades. The goal for the ADRF670X was to keep this level below -75 dBc. To ensure adequate separation between key magnetic circuits, electromagnetic (EM) simulations showed that unshielded spacing must exceed 1400 m while shielded spacing could be as close as 1000 m.

EVM performance can be degraded by noise and distortion in the transmitter. To demonstrate the performance of an ADRF670X RFIC, the ACPR and EVM of the ADRF6702 versus output power are plotted in Fig. 8 for a W-CDMA application at 1940 MHz. Measurements of a four-carrier GSM waveform with the same RFIC reveal IMD of better than -75 dBc at a composite output power of -10.7 dBm.

The ADRF670X and ADRF660X families integrate three low-drop-out (LDO) voltage-regulation circuits that enable high performance from a single +5-VDC supply. The LDOs supply a regulated voltage to the VCO, the charge pump, and to the SDM while the I/Q modulator operates at +5 VDC. Baseband inputs for the ADRF670X and ADRF660X RFICs match the company's TxDAC family of transmit digital- to-analog-converters (DACs). The ADRF670X and ADRF660X RFICs and their associated LDOs are supplied in 6 x 6 mm 40-pin LFCSP-VQ packages.

Analog Devices, Inc., 3 Technology Way, P. O. Box 9106, Norwood, MA 02062; (781) 329-4700, (800) 262-5643, Internet: www.analog.com.