Millimeter-wave components promise to deliver the broadband performance needed for multimedia services. Achieving these services, however, required reliable, low-cost monolithic microwave integrated circuits (MMICs) suitable for millimeter-wave use. Based on the multifunction-self-aligned-gate (MSAG) MESFET process from M/A-COM (Roanoke, VA), a design approach was developed for several Ka-band MMIC power amplifiers. The amplifiers, which delivered several watts of output power at about 25-percent power-added efficiency (PAE) from 26.0 to 27.5 GHz, were fabricated with 0.15-to-0.25-m gate pHEMT processes.1-10

The MSAG process has been used for both commercial and military MMICs.11-16 The MSAG process eliminates the need for a gate recess, the single most important yield and reproducibility limiting step. In this process, the active devices use 0.4-m gates deposited by employing low-cost optical lithography, leading to higher throughput and lower cost. The MSAG process does not use air bridges, has polyimide scratch protection, has multilevel plating capability17-20 for low-loss passive components, has no hydrogen poisoning susceptibility, and is very reproducible unit to unit. These features all lead to higher assembly yields with MSAG chips and provide cost-effective solutions.

Nominal measured performance for MSAG power FETs include a peak drain current (Ip) of 460 mA/mm, saturated drain current (IDSS) of 380 mA/mm, and transition frequency (fT) around 21 GHz. Although the fT is much lower than that of typical pHEMTs, the MSAG FETs have better than 8-dB gain at 30 GHz, due to high output resistance and low feedback capacitance between the gate and drain electrodes. Figure 1 shows a plot for maximum available gain (MAG) versus frequency for a 300-m FET biased at a drain-source voltage (VDS) of = +5 VDC and a gate-source voltage (VGS) of -1.4 VDC. Maximum stable gain at 30 GHz is about 8.7 dB. The peak current values for MSAG FETs is comparable to that of pHEMTs, suggesting that the power density (W/mm of gate periphery) of FETs will be comparable to pHEMTs. The typical performance for an 625-m gate periphery MSAG FET biased for Class AB operation includes +27 dBm output power and 8.4 dB power gain at 14.5 GHz with 60-percent PAE when running from a drain-source voltage of +10 VDC and gate-source voltage of -2 VDC.

At VDS = +8 VDC and 50-percent IDSS, the load resistance value used for Ka-band designs is 31 (omega)/mm and the parallel load capacitance is -0.32 pF/mm. These values were derived by scaling the load impedance value found at 14 GHz and VDS = +10 VDC. The Ka-band load impedance values are very close to the load used in the design of 2- and 4-W Ka-band MMIC power amplifiers.9

Ka-band amplifier designs were based on S-parameters obtained from 0.5 to 40.0 GHz at the operating bias point and load impedance. Designs were optimized using the loadline technique,21-24 with four sets of S-parameter data, corresponding to device low gain, high gain, low current, and high current, used to achieve the desired performance goals. These data files represent possible fabrication changes and help to realize a design that is tolerant to process variations. Both single-stage and three-stage amplifiers were designed.

A single-stage 28-GHz amplifier (Fig. 2) was comprised of a 625-m FET (eight fingers and 20-m gate-gate pitch). The input port was well matched while the output port was matched for maximum output power and gain. The output match loss was about 0.2 dB. A single-stage design was also developed for use at 36 GHz, with relatively narrow (0.5-GHz) bandwidth like the 28-GHz design.

The three-stage design consists of two 300-m FETs at the input driving four 300-m second-stage FETs in turn driving four 625-m output FETs. Both the 300-m (four fingers) and 625-m (eight fingers) FETs have 20-m gate-gate pitch. This amplifier was designed for use from 26 to 29 GHz using a low-loss matching (LLM) technique.25 In this scheme, both the resistive or dissipative loss (DL) and mismatch loss (ML) for each stage are calculated and controlled as required by the design. Generally, the DL and ML for the output match are kept at a minimum and ML for the interstages is minimized. The controlling factors for DL and ML for each intermediate stage include stability criteria and electrical performance. This also helps in optimizing the FET aspect ratios. The DL is for individual passive stages, i.e., interstage, output, etc., while the ML is the difference between the required device's optimum load impedance and the transformed 50-(omega) output impedance at the FET's drain terminal.

For the three-stage amplifier shown in Fig. 3(a), the total loss (TL) for interstage 1, interstage 2, and output stages are given by


D = the dissipative losses (in dB) and
M = the mismatch losses (in dB).

If ZL1, ZL2, and ZL3 are the required optimum load impedance values for the first-, second-, and third-stage FETs, and Z'L1, Z'L2, and Z'L3 are the actual impedance values measured at the drains of the first-, second-, and third-stage FETs looking toward the load, the mismatch losses are



Z*Li = the complex conjugate of ZLi.

When Z*Li @ Z'Li, MLi @ 0 dB. For power amplifiers, large-signal S-parameter data is required for accurate calculation of mismatch losses for interstage networks. However, small-signal S-parameter data for active devices results in approximate solution but acceptable for most applications.25

The dissipative loss for each passive stage is calculated by connecting a complex conjugate impedance at ports connected to FETs. For the input and output matching networks, the dissipative losses are


S = the S-parameters for the respective networks.

For the interstages Fig. 3(b)>, the dissipative losses are calculated using


S = the S-parameters of the jth network,

Gsj and GLj = the simultaneous conjugate match input and output reflection coefficients of interstage j, respectively. For passive networks they are calculated using the following relationships:

The method shown above is based on the assumption that the device input impedance depends strongly on the load connected to its drain terminal rather than its large-signal parameters. For FETs and HEMTs, this assumption is fairly accurate and is the cornerstone of the three-stage design.

In the three-stage amplifier, the input stage, which has a limited gain-compensation network, was designed for good input match as well as for maximum power transfer at high frequencies. The interstage matching networks were designed to provide flat gain response and to deliver enough power to the next stage FETs for achieving overall maximum output power and PAE. Figures 4 and 5 show simulated dissipative loss and the total loss for the interstage 1 and 2 matching networks, respectively. The dissipative loss for each interstage network is adjusted for unconditionally stable operation of each stage. It should be noted that the mismatch loss around 27 GHz is much lower than the dissipative loss. Output matching elements were selected to provide an optimum load match with minimum insertion loss, since efficiency and output power are reduced by passive loss. Figure 6 shows the dissipative loss (less than 0.35 dB) and total loss for the output matching network.

All stages as well as the complete amplifier were designed to be unconditionally stable for a drain supply voltage range of +2 to +8 VDC and 25 to 50 percent saturated-drain-source (Idss) current. Experience has shown that for MSAG FETs standard even-mode (K > 1) and odd-mode stability analyses are adequate to avoid microwave oscillations. However, under large-signal conditions and pulsed operation, it is necessary to use worst-case K-factors greater than 1 when S-parameters data is used for various bias conditions. By imposing a K > 2.0 condition for Vds = +8 VDC and 25 percent Idss, small-signal S-parameters can be used to is ensure K > 1 under all conditions.

Page Title

The MSAG process features a full suite of active and passive components fabricated on 4-in.-diameter GaAs wafers. The process includes 0.4-m TiWN Schottky barrier gates, Au/Ge/Ni metallization for ohmic contacts, thin-film and ion-implanted resistors, metal-insulator-metal (MIM) capacitor and planarized dielectric layers, metal 1 and plated gold conductors, and polyimide dielectric layers. Active layers are defined by selective ion implantation. The process requires an additional mask for each implant, which may include an EFET, a DFET, a low-noise FET, a mixer/limiter diode, a switching FET, a power FET, and n' implants.

The refractory gate metal serves as the implant mask for the source and drain, resulting in a self-aligned FET. Because the gate is present during the high-temperature (+900C) rapid thermal anneal for implant activation, the resulting gate structure is very robust and exhibits extremely high reliability, e.g. a mean-time to failure (MTTF) of 100 years at a channel temperature of +150C. A planarized dielectric layer of SiON is used to passivate the GaAs, exposing only gate features to permit 1-m overlay metal contact for reduced gate resistance. Metal 1 also serves as an interconnect layer and is typically used to form the bottom plate of MIM capacitors. A thickness of 0.2-m silicon-nitride (dielectric constant of 6.8) dielectric film is used for the MIM capacitors. Plated gold provides a second, low-resistance global metallization layer and is used to define capacitor top plates, inductors, microstrip lines, and bond pads.

The process also employs three layers of polyimide (dielectric constant of 3.2); interlevel dielectric (3 m thick), low loss microstrip (10 m thick), and scratch protection buffer layer (7 m thick) for mechanical protection of the finished circuitry. Low capacitance metallization crossovers are achieved by a polyimide intermetal dielectric applied just prior to plating. Front-side processing is completed by the pattering of a polyimide buffer layer. The buffer layer provides mechanical protection of the circuit structures during backside processing, dicing, and subsequent assembly operations. Finally, the wafers are thinned to its final thickness of 75 m, through-wafer via holes (if used) are etched, and the backside is metallized.

The single-stage amplifiers were characterized by measuring CW S-parameters and output power versus input power. The S-parameters were measured on wafer using RF probes at VDS = +5 VDC and VGS = -1 VDC (IDS @ 50 percent IDSS). Figures 7 and 8 show average small-signal CW measured data for the 28- and 36-GHz amplifiers, respectively. Measured gain values were 9.5 dB and 7.0 dB, at 27.5 and 36 GHz, respectively. Power measurements were performed by mounting several amplifier chips on gold-plated carriers and using RF probes at VDS = +8 VDC and VGS = -1 VDC. Figure 9 shows the average CW output power and PAE as a function of input power at 27 GHz for the 28-GHz amplifier. The measured output power, PAE, associated gain, and drain current values at 27 GHz were 282 mW (@ 0.45W/mm of gate periphery), 27 percent, 5.5 dB, and 94 mA, respectively. The measured output power for the 36-GHz power amplifier was +19.8 dBm at 36 GHz.

Figure 10 shows the typical CW measured Pout and PAE for the three-stage MMIC chips on CuW carriers at VDS = +6 VDC and Pin = +17 dBm. The amplifier has greater than +28.0 dBm compressed output power and better than 24-percent PAE over the 26-to-27.5-GHz frequency range. Figure 11 depicts compressed output power levels at various drain voltages. The measure values of output power were better than +27 dBm over the 25.5-to-29-GHz frequency range. The variations of small signal gain and input VSWR as a function of frequency are shown in Fig. 12. The input VSWR is better than 2.5:1 over the 24-to-28-GHz range. Figure 13 shows output power versus input power at various frequencies. At +8 VDC and 27 GHz, the output power is greater than +29.5 dBm.

The author wishes to acknowledge the support of M/A-COM's layout, test, standard microwave products, and wafer-processing groups in the successful development of the MMICs mentioned in this article.


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